11
?
Internal blocks of SRAM, Instruction and Data caches serve to increase data reuse and
availability,
?
Four Independent bi-directional FIFOs or GMACs,
?
Long list of low and high speed peripheral devices - UARTs, High-speed Serial
Peripheral Interface (SPI), GPIO, Generic Interface Bus (GIB) and others.
Stretch SCP is a novel hybrid microprocessor architecture. It combines a well-defined Xtensa
CPU design from the Tensilica, Inc. and two FPGA-like, flexible and re-programmable, wide
data processing devices that implement application-specific processing-intensive algorithmic
kernels as user-programmed Extended Instructions. By processing data items in parallel these
Instruction Set Extension Fabric (ISEF) devices deliver orders of magnitude boost in the data
processing speed just where it is necessary.
Similarly to FPGA, the ISEF units are most effective when processing fixed-point data. Floating-
point data processing should be done using Xtensa built-in 32-bit Floating-Point Unit.
Figure 3 – Stretch S5610 Block Diagram
Xtensa Core
The Xtensa processor core is a modern RISC microprocessor targeted at embedded
applications. Its well defined Instruction Set Architecture (ISA) offers industry-leading code
density, enables high performance and low-power. Even more important that its name reflects
ease with which this ISA can be extended to enable a seamless integration with a tightly
coupled co-processor. Xtensa core runs in a lockstep with its co-processors issuing them
instructions, providing them with data and picking-up results. It can also change their
configuration re-programming them on the fly with a minimal latency to a different set of
operations.
