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[AKD4648-C]
<KM088701>
2007/04
- 8 -
(3-2-4) All interface signals are fed externally
PORT3 (DSP) is used. Nothing should be connected to PORT1 (DIR) and PORT2 (DIT).
BICK, LRCK, and SDTI are supplied from PORT3.
The jumper pins should be set as follows.
(4) PLL
Master
Mode
(4-1) Evaluation of A/D using DIT of AK4115
PORT2 (DIT) and PORT3 (DSP) are used. Nothing should be connected to PORT1(DIR).
The system clock (PLL reference clock) should be connected to MCLK of PORT3.
In case of supplying MCKO to DSP, the JP14 (4115_MCKI)’s lower side should be connected to MCLK of DSP.
X’tal oscillator should be removed from X1.
In Master Mode, BICK and LRCK of AK4648 should be input to AK4115. Please refer to Table2 on page 11.
The jumper pins should be set as follows.
(4-2)
Evaluation
of
Loop-back
PORT2 (DIT) and PORT3 (DSP) are used. Nothing should be connected to PORT1(DIR).
The system clock (PLL reference clock) should be connected to MCLK of PORT3.
In case of supplying MCKO to DSP, the JP14 (4115_MCKI)’s lower side should be connected to MCLK of DSP.
X’tal oscillator should be removed from X1.
The jumper pins should be set as follows.
JP17
LRCK
JP16
BICK
JP15
DIR_MCLK
JP14
4115_MCKI
JP19
DIR_SEL
Master
Slave
JP21
SDTI
ADC
DIR
JP20
SDTO_IN
JP2
RIN3
VCOC
JP17
LRCK
JP16
BICK
JP15
DIR_MCLK
JP14
4115_MCKI
JP19
DIR_SEL
Master
Slave
JP21
SDTI
ADC
DIR
JP20
SDTO_IN
JP2
RIN3
VCOC
JP17
LRCK
JP16
BICK
JP15
DIR_MCLK
JP14
4115_MCKI
JP19
DIR_SEL
Master
Slave
JP21
SDTI
ADC
DIR
JP20
SDTO_IN
JP2
RIN3
VCOC