akira LCT-37KX1DSTP, Service Manual

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Multistandard video decoder with adaptive
comb filter and component video input
SAA7117(A)H/V2
SAA7117(A)E/V2
AI11 27 J2 I analog input 11
V
SSA1
28 J4 P ground for analog inputs AI1x
AI12 29 K1 I analog input 12
AI1D 30 K3 I differential input for ADC channel 1 (pins AI14 to AI11)
AI13 31 K2 I analog input 13
V
DDA1
32 K4 P analog supply voltage for analog inputs AI1x (3.3 V)
V
DDA1A
33 L1 P analog supply voltage for analog inputs AI1x (3.3 V)
AI14 34 L3 I analog input 14
AGNDA 35 L2 P analog signal ground
DNC 36 M1 NC do not connect, reserved for future extensions and for testing
V
DDA0
37 M3 P analog supply voltage (3.3 V)
V
SSA0
38 M2 P analog ground
AOUT 39 N1 O analog output (7117A only)
VDDA_C18 40 N2 P analog supply voltage (1.8 V)
VDDA_A18 41 P2 P analog supply voltage (1.8 V)
DNC15 42 N3 I do not connect, reserved for future extensions and for testing
GPIN 43 P3 I/pu general purpose input (with internal pull-up)
CE 44 N4 I/pu chip enable or reset input (with internal pull-up)
V
DDD1
45 M4 P digital supply voltage 1 (peripheral cells, 3.3 V)
LLC 46 P4 O line-locked system clock output (27 MHz nominal)
V
SSD1
47 L4 P digital ground 1 (peripheral cells)
LLC2_54 48 N5 O line-locked
1
/
2
clock output (13.5 MHz nominal), or adc_clock 54 MHz,
selectable via I
2
C
RES 49 P5 O reset output (active LOW)
V
DDD2
50 M5 P digital supply voltage 2 (core, 1.8 V)
V
SSD2
51 L5 P digital ground 2
DNC23 52 N6 I do not connect, reserved for future extensions and for testing
DNC24 53 P6 O do not connect, reserved for future extensions and for testing
DNC25 54 M6 O do not connect, reserved for future extensions and for testing
DNC26 55 L6 O do not connect, reserved for future extensions and for testing
DNC27 56 N7 O do not connect, reserved for future extensions and for testing
DNC28 57 P7 O do not connect, reserved for future extensions and for testing
DNC29 58 L7 O do not connect, reserved for future extensions and for testing
V
DDD3
59 M8 P digital supply voltage 3 (peripheral cells, 3.3 V)
DNC30 60 M7 O do not connect, reserved for future extensions and for testing
DNC31 61 P8 O do not connect, reserved for future extensions and for testing
DNC32 62 N8 O do not connect, reserved for future extensions and for testing
V
SSD3
63 L8 P digital ground 3 (peripheral cells)
INT_A 64 P9 O/od I
2
C-bus interrupt flag (LOW if any enabled status bit has changed)
V
DDD4
65 M9 P digital supply voltage 4 (core, 1.8 V)
SYMBOL
PIN
TYPE
(1)
DESCRIPTION
QFP160 BGA156