5.4 LVDS INTERFACE
8bit LSB: R0, G0, B0
JEIDA: Parallel TTL Data Inputs Mapped to LVDS outputs
TRANSMITTER(THC63LVD823)
INTERFACE
CONNECTOR
PIN NO
INPUT DATA
HOST
TFT_LCD
TIMING CONTROLLER INPUT
51 TA0
R2
52 TA1
R3
54 TA2
R4
55 TA3
R5
56 TA4
R6
3 TA5
R7
(MSB)
4 TA6
TxOUT0-
TA+
TA-
G2
6 TB0
G3
7 TB1
G4
11 TB2
G5
12 TB3
G6
14 TB4
G7
(MSB)
15 TB5
B2
19 TB6
TxOUT1-
TB+
TB-
B3
20 TC0
B4
22 TC1
B5
23 TC2
B6
24 TC3
B7
(MSB)
27 TC4
Hsync
28 TC5
Vsync
30 TC6
TxOUT2-
TC+
TC-
DENA
50 TD0
R0
(LSB)
2 TD1
R1
8 TD2
G0
(LSB)
10 TD3
G1
16 TD4
B0
(LSB)
18 TD5
B1
25 TD6
TxOUT3-
TD+
TD-
Reserved
58