Akai ADP-841, Service Manual

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MP1410
2A Step-Down
Switch-Mode Regulator
MP1580 Rev 1.4 Monolithic Power Systems, Inc. 4
04/01/02 3777 Stevens Creek Blvd, Suite 400, Santa Clara, CA 95051-7364 USA
© 2002 MPS, Inc. Tel: (408) 243-0088, Fax: (408) 243-0099, Web: www.monolithicpower.com
Monolithic Power Systems
Pin Functions
BS (Pin 1) Bootstrap
This capacitor is needed to drive the power
switch’s gate above the supply voltage. It is
connected between V
SW
and Bootstrap pins to
effect a floating supply across the power switch
driver. The voltage across C
B
is about 5V and is
supplied by the in5V supply when the V
SW
pin voltage is low.
V
IN
(Pin 2) Supply Voltage
The MP1580 operates from a +4.75 to +25V
unregulated input. C
IN
is needed to prevent large
voltage spikes from appearing at the input.
V
SW
(Pin 3) Switch
This connects the inductor to either the V
IN
through
M1 or to GND through M2.
GND (Pin 4) Ground
This pin is the voltage reference for the regulated
voltage. For this reason care must be taken in its
layout. This node should be placed outside of the
D
SCH
to C
IN
ground path to prevent switching
current spikes to induce voltage noise into the
part.
FB (Pin 5) Feedback
An external resistor divider from the output voltage
to GND, tapped to the FB pin sets the output
voltage. To prevent current limit run away during
a short circuit fault condition the frequency
foldback comparator lowers the oscillation
frequency when the FB voltage is below 650mV.
COMP (Pin 6) Compensation
This node is the output of the transconductance
error amplifier and the input to the current
comparator. Frequency compensation is done at
this node by connecting a series R-C to ground.
See the compensation section for exact details.
EN (Pin 7) Enable/UVLO
A voltage greater than 2.495V enables operation.
Leave the input unconnected if unused. An Under
Voltage Lockout (UVLO) function can be
implemented by the addition of a resistor divider
from Vin to GND. For complete low current
shutdown its needs to be less than 0.7V.
SYNC (Pin 8) Synchronization Input
This pin is used to synchronize the internal
oscillator frequency to an external source. There
is an internal 11kohm pull down resistor to GND
hence leave the input unconnected if unused.
Sync Pin Operation.
The Sync pin driving waveform should be a square
wave with a rise time of less than 20ns. Minimum
Hi voltage level is 2.7V.
Low level is less than
0.8V. The frequency of the external Sync signal
needs to be greater than 445 kHz.
A rising edge on the Sync pin forces a reset of the
oscillator. The the upper DMOS is switched off
immediately if it is not already off. 250nS later the
upper DMOS turns on connecting Vsw to Vcc.
BS 1
2
3
4 5
6
7
8
V
IN
V
SW
GND
SYNC
EN
COMP
FB