– 34 –
39
CV–
I
Input for CLV error signal from DSP.
40
CV+
41
RFSM
O
Output for RF.
42
RFS–
O
For setting RF gain and 3T compensation constant together with RFSM.
43
SLC
O
SLICE LEVEL CONTROL; output for controlling the data slice level of DSP with
RF waveform.
44
SLI
I
Input for controlling the data slice level of DSP.
45
D-GND
–
GND for digital system.
46
FSC
O
Output pin for focus search smoothing capacitor.
47
TBC
I
(Tracking Balance Control) EF balance variable range setting pin.
48
NC
–
Not connected.
49
DEF
O
Output for disk defect detection.
50
CLK
I
Standard clock input; DSP's 4.23MHz is inputted.
51
CL
I
Clock input for microcontroller command.
52
DAT
I
Data input for microcontroller command.
53
CE
I
Chip-enable input for microcontroller command.
54
DRF
O
Detect RF; output for RF level detection.
55
FSS
I
(Focus Search Mode) = search against reference voltage switching pin. (Not used)
56
VCC2
–
VCC pin for servo and digital systems.
57
REFI
I
For connecting pass capacitor to reference voltage.
58
VR
O
Reference voltage output.
59
LF2
–
For setting disk defect-detection time constant.
60
PHI
–
Connects to capacitor for RF signal peak hold.
61
BHI
–
Connects to capacitor for RF signal bottom hold.
62
LDD
O
Output for APC circuit.
63
LDS
I
Input for APC circuit.
64
VCC1
–
VCC pin for RF system.
Pin No.
Pin Name
I/O
Description
www.freeservicemanuals.info
9/3/2014
Global electronic heritage manuals
