Pin No.
Pin Name
I/O
Description
-64-
IC DESCRIPTION - 8/12 (ZIVA4.1) - 4/5
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
180
181
182 ~ 184
185 ~ 187
188
VCLK
A_VDD
DVD-DATA0/CD-DATA
DVD-DATA1/
CD-LRCK
DVD-DATA2/
CD-BCK
DVD-DATA3/
CD-C2P0
DVD-DATA4/
CDG-SDATA
VSS
VDD_3.3
DVD-DATA5/
CDG-VFSY
DVD-DATA6/
CDG-SOS1
DVD-DATA7/
CDG-SCLK
VDACK
VREQUEST
VSTROBE
RESERVED
NC
HADDR0 ~ HADDR2
RESERVED
VSS
I
–
I
I
I
I
I
–
–
I
I
I
I
O
I
I
I
I
–
I
I
–
Video clock. Clocks out data on input. VDATA[7:0]. Clock is typically 27 MHz.
System clock that drives internal PLLs and internal DENC. ZiVA-4 requires an external 27-MHz
TTL oscillator.
3.3-V Analog PLL Power
Serial CD data. This pin is shared with DVD compressed data DVD-DATA0.
Programmable polarity 16-bit word synchronization to the decoder (right channel HIGH). This
pin is shared with DVD compressed data DVD-DATA1.
CD bit clock. Decoder accept multiple BCK rates. This pin is shared with DVD compressed data
DVD-DATA2.
Asserted HIGH indicates a corrupted byte. Decoder keeps the previous valid picture on-screen
until the next valid picture is decoded. This pin is shared with DVD compressed data DVD-
DATA3.
DVD parallel compressed data from DVD DSP. Or CD+G (Subcode) data indicating serial
subcode data input.
Ground for core logic and I/O signals.
3.3-V supply voltage for I/O signals.
DVD parallel compressed data from DVD DSP. Or CD+G (Subcode) Frame Sync indicating
frame-start or composite synchronization input.
DVD parallel compressed data from DVD DSP. Or CD+G (Subcode) Block Sync indicating
block-start synchronization input.
DVD parallel compressed data from DVD DSP. Or CD+G (Subcode) Clock indicating subcode
data clock input or output.
In synchronous mode, bitstream data acknowledge. Asserted when DVD data is valid. Polarity is
programmable.
Bitstream request. Decoder asserts VREQUEST to indicate that the bitstream input buffer has
available space. Polarity is programmable.
Bitstream strobe. Programmable dual mode pulse. Asynchronous and synchronous. In
Asynchronous mode, an external source pulses VSTROBE to indicate data is ready for transfer.
In synchronous mode, VSTROBE clocks data.
Error in input data. If ERROR signal is not available from the DSP it must be grounded.
3.3-V supply voltage for I/O signals.
Tie to VSS or VDD_3.3
3.3-V supply voltage for I/O signals.
Ground for core logic and I/O signals.
Not used
Tie to VSS or VDD_3.3
Not used
Host address bus. 3-bit address bus selects one of eight host interface registers.
Tie to VSS or VDD_3.3
Ground for core logic and I/O signals.
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