–
20
–
1
Y OUT
O
The output pin for Y signal.
2
MODE SW
O
The pin for controlling the Y processing mode:
to Vcc: 5.5MHz trap ; open: 5.5MHz trap + D.L ; to GND: DL. (not used)
3
R-Y OUT
O
The output pin for demodulated R-Y signal.
4
R-Y BLACK CONTROL
I
The pin for controlling the black offset level. (not used)
5
B-Y OUT
O
The output pin for demodulated B-Y signal.
6
B-Y BLACK CONTROL
I
The pin for controlling the black offset level. (not used)
7
S-ID FILTER
I
The pin for connecting the SECAM ident filter capacitor.
8
EXT R-Y IN
I
The input pin for external R-Y signal. (not used)
9
5V VCC
-
The Vcc pin for Y/C processing block.
10
EXT B-Y IN
I
The input pin for external B-Y signal. (not used)
11
GND
-
The Gnd pin.
12
Fo-ADJ FILTER
I
The pin for connecting a capacitor for automatic adjusting circuit.
13
C IN
I
The chroma signal input pin.
14
BELL-ADJ FILTER
I
The pin for connecting a capacitor for the bell filter fo, 4.286MHz.
15
Y IN
I
The Y signal input pin.
16
BELL CONTROL
I
The pin for selecting the bell filter fo.
fo + 70KHz: open ; fo + 35KHz : 20k to GND ; fo: to GND.(Connected to Pin 18)
17
S.C.P. IN
I
The pin to input the sand castle pulse, SCP.
18
5V VCC
-
Vcc pin for logic block.
19
4.43MHz CW IN
I
The pin for input 4.43MHz of carrier wave for self adjustment circuit.
20
ID SW
I
The switch pin for selecting the ID detection mode. (Connected to Pin 18)
H + V: connected to Vcc ; Auto search: opened ; H: connected to GND.
21
SECAM ID I/O
I/O
The interface pin to the main processor.
Pin No.
Pin Name
I/O
Description
IC, TA1275AZ
Summary of Contents for TV-C143
Page 8: ...SCHEMATIC DIAGRAM MAIN NK 8...
Page 11: ...IC BLOCK DIAGRAM IC STR S6706 11...