-33-
FOK
FSW
MON
MDP
MDS
LOCK
NC
VCOO
VCOI
TEST
PDO
VSS
PWMI
V16M
VCTL
VPCO
VCKI
FILO
FILI
PCO
AVSS
CLTV
AVDD
RF
BIAS
ASYI
ASYO
ASYE
NC
PSSL
WDCK
LRCK
VDD
DATA
BCK
DATA64
BCK64
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
IC, CXD2540Q
Pin No.
Pin Name
I/O
Description
I
O
O
O
O
O
—
O
I
I
O
—
I
O
I
O
I
O
I
O
—
I
—
I
I
I
O
I
—
I
O
O
—
O
O
O
O
Focus OK input. Used for SENS output and the servo auto sequencer.
Spindle motor output filter switching output. (Not connected)
Spindle motor on/off control output. (Not connected)
Spindle motor servo control.
Spindle motor servo control. (Not connected)
High, when sampled value of GFS at 460Hz is high.
Low, when sampled value of GFS at 460Hz is low by 8 times successively.
Not used.
Analog EFM PLL oscillation circuit output. (Not connected)
Analog EFM PLL oscillation circuit input. fLOCK=8.6436MHz. (Connected to ground)
TEST pin. (Connected to ground)
Analog EFM PLL charge pump output. (Not connected)
GND. (Connected to ground)
Spindle motor external control input. (Connected to ground)
VCO2 oscillation output for the wide-band EFM PLL.
VCO2 control voltage input for the wide-band EFM PLL.
Wide-band EFM PLL charge pump output.
VCO2 oscillation input for the wide-band EFM PLL.
Multiplier PLL (slave=digital PLL) filter output.
Multiplier PLL filter input.
Multiplier PLL charge pump output.
Analog GND.
Multiplier VCO1 control voltage input.
Analog power supply (5V).
EFM signal input.
Constant current input of the asymmetry circuit.
Asymmetry comparator voltage input.
EFM full-swing output.
Low: asymmetry circuit off; high: asymmetry circuit on.
Not used.
Audio data output mode switching input. Low: serial output; high: parallel output. (Connected to
ground)
D/A interface for 48-bit slot. Word clock f=2Fs. (Not connected)
D/A interface for 48-bit slot. LR clock f=Fs.
Power supply (5V).
DA16 (MSB) output when PSSL=1.
48-bit slot serial data (two’s complement, MSB first) when PSSL=0.
DA15 output when PSSL=1. 48-bit slot bit clock when PSSL=0.
DA14 output when PSSL=1.
64-bit slot serial data (two’s complement, LSB first) when PSSL=0. (Not connected)
DA13 output when PSSL=1. 64-bit slot bit clock when PSSL=0. (Not connected)
IC DESCRIPTION
Summary of Contents for LCX-K117
Page 12: ... 12 SCHEMATIC DIAGRAM 1 MAIN 2B 1 2 DECK 2B Q243 244 ...
Page 13: ... 13 SCHEMATIC DIAGRAM 2 MAIN 2B 2 2 2B ...
Page 16: ... 16 SCHEMATIC DIAGRAM 3 VCD 1 2 2B ...
Page 17: ... 17 SCHEMATIC DIAGRAM 4 VCD 2 2 DAC_CK V ID ...
Page 18: ... 18 SCHEMATIC DIAGRAM 5 FR LED 2B D ...
Page 20: ... 20 SCHEMATIC DIAGRAM 6 PT PTX901 ...
Page 24: ... 24 FL AIWA4239ACL 13 GRID ASSIGNMENT ANODE CONNECTION GRID ASSIGNMENT ANODE CONNECTION ...
Page 25: ... 25 VOLTAGE CHART ...
Page 26: ... 26 ...
Page 27: ... 27 ...
Page 28: ... 28 ...