22
1
SVDD
Sensing power (+5V) pin.
2
RESET
I
Chip reset. Active high.
3AGCEN
I
AGCEN = 1 enables the Auto Gain Control. AGCEN = 0 disables it.
This pin setting is effective when pin IICB = 1. (Not used)
4
FREX
I
Frame exposure control input, effective in progressive scan only.
The positive width of FREX defines the exposure time. (Not used)
5
VREQ
Internal voltage reference. Requires an 0.1uF decoupling capacitor to ground.
Analog ground connections.
Analog power (+5V) pin.
I
PWDN = 1 puts chip in power down (sleep) mode.
Internal voltage reference. Requires an 0.1uF decoupling capacitor to ground.
Internal voltage reference. Requires an 0.1uF decoupling capacitor to ground.
IICB = 1 selects the power-up method of programming the internal functions.
I
IICB = 0 selects the I
2
C pin programming method. Results of the power-up method
can only be changed by a new power-up or reset sequence. (Not used)
13VTO
O
Video test output (NTSC).
14
AVDD
Analog power (+5V) pin.
15
AGND
Analog ground connection.
16
VSYNC
O
VSYNC: Vertical sync output.
This pin is asserted high during several scan lines in the vertical sync period
49
SIBD
I
Serial input data. Interface B. (Connected to ground)
50
SIBC
I
Serial input clock. Interface B. (Connected to ground)
51
SIBI
I
Serial input frame identification. Interface B. (Connected to ground)
52
SPDI2
I
Active differential S/PDIF input 2. (Not used)
53SPDI1
I
Active differential S/PDIF input 1. (Not used)
54
SPDIR
I
Reference differential S/PDIF input 1 and 2. (Not used)
55
FILTL
I
Feedback input for left amplifier.
56
AVDD0
Analog supply for output amplifiers.
57
OUTL
O
Left analog output.
58
OUTR
O
Right analog output.
59
AVSS0
Analog ground for output amplifiers.
60
FILTR
I
Feedback for right output amplifiers.
61
AVSS1
Analog ground.
62
VREF
Analog reference ground.
63PVDD
Internal power supply.
64
AVDD1
Analog supply.
Pin No.
Pin Name
I/O
Description
IC, OV7620
Pin No.
Pin Name
I/O
Description
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