Pin No.
Pin Name
I/O
Description
43
89
90
91
92, 93
94
95
96
97
98 ~ 100
POWER FAIL
IIC
IIC
NC
FLD ENABLE
FLD CLOCK
FLD DATA IN
FLD DATA OUT
NC
I
O
O
–
O
O
I
O
O
1. When a power failure is detected, this pin goes “L” and the following sequence of
events occurs.
2. Power failure detector timing sequence.
A reference CLOCK for Hi-Fi, TU/IF, MTS, SPEAKER
A reference DATA for Hi-Fi, TU/IF, MTS, SPEAKER
Not connect
Outputs chip enable signal for FLD Drive IC (IC5F1).
Outputs clock signal to operate FLD Drive IC (IC5F1).
Serial interface signals for FLD Drive IC control.
Not connect
AC POWER ON
AC POWER OFF
t
t
t
t
t
t
Power failure
compensation cancel state
Power failure
compensation
state
(
µ
-COM memory loss state)
Vcc for (Back-up)
AVcc No (Back-up)
Power failure signal
10MHz OSC
36.768kHz OSC
Reset pulse
Power failure
compensation relation
Normal
operation
state
5.3VA
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9
9
2
8
9
4
2
9
8
TEL 13942296513
9
9
2
8
9
4
2
9
8
0
5
1
5
1
3
6
7
3
Q
Q
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