Aiwa CSD-FD73 HC, Service Manual

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Pin No. Pin Name I/O Description
38 LVSS – Left channel one-bit D/A converter ground. (Must be connected to 0V.)
39 RVSS - Right channel one-bit D/A converter ground. (Must be connected to 0V.)
40 RCHO O Right channel one-bit D/A converter output.
41 RVDD - Right channel one-bit D/A converter power supply.
42 MUTER O Right channel one-bit D/A converter mute output. (not used)
43 XVDD - Crystal oscillator power supply.
44 XOUT O
Connections for a 16.93 MHz crystal oscillator element.
45 XIN I
46 XVSS - Crystal oscillator ground. (Must be connected to 0V.)
47 SBSY O Subcode clock synchronization signal output. (not used)
48 EFLG O C1, C2, sigle an double error correction monitor. (not used)
49 PW O Subcode P, Q, R, S, T, U and W output. (not used)
50 SFSY O
Subcode frame synchronization signal output. This signal falls when the subcode are
in standby state. (not used)
51 SBCK I Subcode readout clock input. This is a Schmitt input. (Must be connected to 0V.)
52 FSX O Output pin for the 7.35 kHZ synchronization signal divided from the crystal oscillator. (Not used)
53 WRQ O Subcode Q output standby output.
54 RWC I Read/write control input. This is a Schmitt input.
55 SQOUT O Subcode Q output.
56 COIN I Command input pin from control microprocessor.
57 CQCK I
Input for both the command input acquisition clock and the SQOUT pin subcode
readout clock input pin. This is Schmitt input.
58 RES I Reset input. This pin must be set low briefly after power is first applied.
59 T11 O Test output. Leave open. (Normally output a low level). (Not used)
60 16M O 16.9344 MHz output. (Not used)
61 4.2M O 4.2336 MHz output.
62 T5 I Test input. A pull-down resistor is built-in. (Must be connected to 0V.)
63 CS I
Chip seledt input. A pull-down resistor is built-in.
(Must be connected to 0V if not controlled.)
64 T1 I Test input. No pull-down resistor. (Must be connected to 0V.)