Aiwa CSD-A310 EZ' CSD-A310 G, Service Manual, Page: 19 / 31

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36 LVDD – Lch power supply.
37 LCHO O Lch output.
38 LVSS – Lch ground. Normally, 0V.
39 RVSS – Rch 1-bit DAC/Rch ground. Normally, 0V.
40 RCHO O Rch output.
41 RVDD – Rch power supply.
42 MUTER O Rch muting output. (Not used)
43 XVDD – Power supply of crystal oscillator.
44 XOUT O
For the connection of a 16.9344 MHz crystal oscillator.
45 XIN I
46 XVSS – Ground of crystal oscillator. Normally, 0V.
47 SBSY O Subcode block sync signal output. (Not used)
48 EFLG O C1,C2,single,duplex correction monitor. (Not used)
49 PW O Output of subcodes P,Q,R,S,T,U and W. (Not used)
50 SFSY O Subcode frame sync signal output. Falls when the subcode is set to the standby state.(No used)
51 SBCK I Subcode read-out clock input. Schmitt trigger input.("L" is applied when not used.)
52 FSX O 7.35 kHz sync signal output obtained by dividing the oscillator frequency. (Not used)
53 WRQ O Subcode Q standby output.
54 RWC I Read/write control input. Schmitt trigger input.
55 SQOUT O Subcode Q output.
56 COIN I Command input from the microprocessor.
57 CQCK I
Command input retrieval clock or subcode retrieval clock input from SQOUT. Schmitt trigger
input.
58 RES I LC78622 reset input.
59 T11 O Test output. Set to open (normally, "L" output.) (Not used)
60 16M O 16.9344 MHz output. (Not used)
61 4.2M O 4.236 MHz output.
62 T5 I Test input. A pull-down resistor is incorporated. Be sure to connect to 0 V.
63 CS I Chip select input. A pull-down resistor is incorporated.
64 TEST1 I Test input with no pull-down resistor. Be sure to connect this to 0 V.
I/O Description
Pin No.
Pin Name