Aiwa 6ZG-1S, Manual

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17
Output terminal for focus error amplifier. Internally connected to window comparator
input for bias condition.
Input terminal for focus error.
Capacitor connection terminal for time constant used when there is defect.
This pin is connected to GND via capacitor when high frequency gain of the focus
servo is attenuated.
This is a pin where the time constant is externally connected to raise the low frequency
gain of the focus servo.
Focus drive output.
Focus amplifier inverted input pin.
This is a pin where the time constant is externally connected to generate the focus
search waveform.
This is a pin where the selection time constant is externally connected to set the
tracking servo the high frequency gain.
This is a pin where the selection time constant is externally connected to set the
tracking high frequency gain.
Pin for setting peak of the phase compensator of the focus tracking.
Tracking amplifier inverted input pin.
Tracking drive output.
Sled amplifier non-inverted input pin.
Sled amplifier inverted input pin.
Sled drive output.
The current which determines height of the focus search, track jump and sled kick is
input with external resistance connected.
Power supply.
“L” setting starts sled disorder-prevention circuit. (Not pull-up resistance)
Clock input for serial data transfer from CPU. (No pull-up resistance)
Latch input from CPU. (No pull-up resistance)
Serial data input from CPU. (No pull-up resistance)
Reset system at “L” setting. (No pull-up resistance)
Signal output for track number counting.
FZC, DFCT1, TZC, BALH, TGH, FOH, or ATSC is output depending on the
command from CPU.
DFCT2, MIRR, BALL, TGL or FOL is output depending on the command from CPU.
Output terminal for focus OK comparator.
Input pin where the DEFECT bottom hold output is capacitance coupled.
DEFECT bottom-hold output terminal. Internally connected to interruption comparator
input.
Connection terminal for DEFECT bottom-hold capacitor.
Connection terminal for MIRR hold-capacitor.
Anti-reverse input terminal for MIRR comparator.
FEO
FEI
FDFCT
FGD
FLB
FE_O
FEM
SRCH
TGU
TG2
FSET
TA_M
TA_O
SL_P
SL_M
SL_O
ISET
Vcc
LOCK
CLK
XLT
DATA
XRST
C_OUT
SENS1
SENS2
FOK
CC2
CC1
CB
CP
IC, CXA1992AR
Pin No. Pin Name I/O Description
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
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IC DESCRIPTION
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