Agilent Technologies J-BERT N4903B, User Manual, Page: 146 / 572

3
Select the trigger pattern that you want to be generated.
See
“ Trigger/Ref Clock Output - Reference” on page 146“ Aux Data Output -
Reference” on page 154 for descriptions of the available trigger signals.
N O T E
If you have downloaded a user-defined sequence of patterns to the pattern
generator, the pattern-related settings are ignored. In this case, you can either set
up the Trigger/Ref Clock Out port to generate a subrate of the present clock or to
signal the beginning of a sequence block (see also
“Sequence Block Parameters”
on page 102 for details).
Trigger/Ref Clock Output - Reference
You can always generate a divided clock signal at the Trigger/Ref Clock Out port.
But if you wish to use the Trigger/Ref Clock Out port for controlling external
equipment, please note that you can also generate a divided clock signal at the
pattern generator's Aux Data Out port.
The alternate trigger signals refer to patterns and are not generated in sequence
mode.
To support the generation of a trigger spike at the beginning of a sequence block,
the Trigger/Ref Clock Output can be put into Sequence mode.
Clock Divided by n
Select this option to send a trigger signal from the Trigger/Ref Clock Out port at
every nth clock pulse. Note that the trigger signal itself consists of n/2 bits high
followed by n/2 bits low. For example,
Clock divided by 8
works as shown below.
Clock
Trigger Out
N O T E
If the Divider Factor n is uneven (For example 3), the clock's duty cycle will not be
50%, but the signal will stay high for (n+1)/2 and low for (n-1)/2. This results in a
Duty Cycle Distortion (DCD) of 0.5 UI.
4
Setting up the Pattern Generator
146 Agilent J-BERT N4903B High-Performance Serial BERT