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Agilent Technologies HDMP-3001, Datasheet

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Agilent Technologies HDMP-3001 Datasheet Download Page 121

121

APPROX. 750 ns

E1, E2, F1

B1

B2

B3

B4

B5

B6

B7

B8

RX_FRAME_SFP

RX_SONETCLK

RX_E1E2F1_CLK

Figure 44. Receive Overhead Clock and Data Alignment

The receive overhead alignment timing diagram (Figure 44) shows the relationship between the
RX_E1_DATA, RX_E2_DATA and RX_F1_DATA serial data outputs and their associated clock
RX_E1E2F1_CLK. It is a 72 kHz 50% duty cycle clock that is gapped to produce a 64 kHz nominal rate
and is aligned as shown in Figure 44.

Summary of Contents for HDMP-3001

Page 1: ...ace Descriptions 17 3 2 1 Microprocessor Interface 17 3 2 2 MII Management Interface 17 3 2 3 EEPROM Interface 17 3 2 4 MII Interface 17 3 2 5 SONET SDH Interface 18 3 3 Initialization 18 3 3 1 Hardwa...

Page 2: ...rs 56 5 4 SONET SDH Receive Registers 61 5 5 Ethernet Transmit Registers 79 5 6 Ethernet Receive Registers 88 6 Package Specification 104 7 Electrical and Thermal Specifications 107 7 1 Technology 107...

Page 3: ...11 Always Enabled Active 1 39 Figure 24 Package Marking 104 Figure 25 Top View of Package 104 Figure 26 Bottom View of Package 105 Figure 27 Side View of Package 105 Figure 28 Detailed View of Pin 105...

Page 4: ...figuration 39 Table 16 Pin Connections MPC860 40 Table 17 Pin Connections MII Interface 41 Table 18 MII Management Register Map 42 Table 19 HDMP 3001 Register Map 44 Table 20 G1 values 59 Table 21 STS...

Page 5: ...SOR ETHERNET MII INTERFACE TO SYSTEM TX FIFO RX FIFO E1 E2 F1 AND DCC E1 E2 F1 AND DCC 8 BIT GENERIC MICROPROCESSOR BUS ETHERNET MANAGEMENT BUS STANDARD 2 WIRE EEPROM BUS 4 BITS AT 25MHz 4 BITS AT 25M...

Page 6: ...ons ANSI T1 105 and ITU G 707 Serial data channels for add and drop of SONET overhead bytes E1 E2 F1 and DCC 8 bit microprocessor interface allows direct connection to the Motorola MPC860 AGILENT FIBE...

Page 7: ...TA 0 RX_DATA 1 RX_DATA 2 RX_DATA 3 RX_DATA 4 BUSMODE1 GND RX_DATA 5 RX_DATA 6 RX_DATA 7 RX_E1E2F1_CLK RX_F1_DATA RX_E2_DATA RX_E1_DATA DVDD DGND DGND DVDD D 7 D 6 D 5 D 4 D 3 D 2 D 1 GND DGND D 0 ADDR...

Page 8: ...indication If RX_OOF_OUT is active continuously for 24 consecutive frames 3 ms the RX_LOF bit is set high Once RX_LOF is set it remains high until RX_OOF_OUT is inactive continuously for 3 ms RX_LOS...

Page 9: ...s also used to monitor the TX_SONETCLK and RX_SONETCLK The requirement for this clock is 25 MHz 100 ppm P_TX_CLK_M_RX_CLK 104 I O Int PU PHY mode transmit clock output Derived from SYS_25M_CLK MAC mod...

Page 10: ...FRAME_SFP RX_FRAME_SFP 158 O RECEIVE FRAMER START OF FRAME INDICATION This signal is nominally 8 kHz and is high during the first row of overhead of the received frame The RX_FRAME_SFP signal is also...

Page 11: ...Data Communications Channel DCC to be inserted by the HDMP 3001 into the outgoing SONET data stream TX_LDCC_CLK 124 O TRANSMIT LINE DCC REFERENCE CLOCK A 576 kHz clock reference for Line DCC data to b...

Page 12: ...TERFACE MODE BUSMODE1 30 BUSMODE1 BUSMODE0 00 Motorola MPC860 mode BUSMODE1 BUSMODE0 01 Reserved BUSMODE1 BUSMODE0 10 Reserved BUSMODE1 BUSMODE0 11 Reserved Both pins are latched at reset and are also...

Page 13: ...ore being tristated Refer to microprocessor application notes for board pull up requirements RSTB 85 I RESET Active low input to reset the HDMP 3001 WRB 54 I WRITE ENABLE Active low Signal name Pin Ty...

Page 14: ...ERAL PURPOSE I O The GPIO register allows the GPIO 1 12 user to define each grouping GPIO 0 1 GPIO 2 3 GPIO 4 5 GPIO 2 13 GPIO 6 7 GPIO 8 9 GPIO 10 11 GPIO 12 13 GPIO 3 14 GPIO 14 15 as either input o...

Page 15: ...pins should be connected to the 1 8 V 42 51 power supply for logic 62 82 91 102 122 131 142 DVDD 19 39 Driver POWER These pins should be connected to the 3 3 V 59 79 power supply for I O 99 119 139 15...

Page 16: ...ee INT Pin Configuration Section RDYB Uses a T S output buffer and logically drives high before output buffer is released or tristated Input TMS TRSTB TDI w Internal P U P_TX_CLK_M_RX_CLK P_RX_CLK_M_T...

Page 17: ...or Interface The interface consists of eight data bits nine address bits three control signals and one acknowl edge signal Through this interface the HDMP 3001 internal register map can be accessed On...

Page 18: ...onally equivalent to hardware resets There are two identical software resets one in the microprocessor register map and one in the MII register map Both resets are self cleared in less than 10 s 3 3 3...

Page 19: ...3 2 1 0 F L 7 0 PINS 7 6 5 4 3 2 1 0 F X24 X31 7 6 5 4 3 2 1 0 X16 X23 7 6 5 4 3 2 1 0 X8 X15 7 6 5 4 3 2 1 0 L X0 X7 Figure 6 LAPS Payload Bit Order Figure 7 LAPS FCS Bit Order clears the bit If a c...

Page 20: ...orted in PHY mode i e when the HDMP 3001 drives the MII clocks TX TX_LAPS RX RX_LAPS F I F O OVERHEAD MII 4 3 THIRD LOOPBACK OUTSIDE CHIP 1 2 Figure 8 Loopbacks The loopback modes are selected by prog...

Page 21: ...e of the interrupt Instruction Opcode Description EXTEST 00 Board Level Interconnection Testing SAMPLE PRELOAD 02 Snapshots of Normal Operation BYPASS FF Normal Chip Operation HIGHZ 08 Outputs in High...

Page 22: ...a 32 bit FCS field Address Control and SAPI PREAMBLE START OF FRAME DELIMITER DESTINATION ADDRESS DA SOURCE ADDRESS SA LENGTH TYPE MAC CLIENT DATA FCS 7 OCTETS 1 OCTET 6 OCTETS 6 OCTETS 2 OCTETS 46 15...

Page 23: ...ion inter packet fill and scrambling The GFP Processor performs the following functions Counts the Ethernet frame length Calculates the payload length field PLI Performs XOR with values as shown in Fi...

Page 24: ...nto the SONET SDH SPE VC The POH and TOH SOH are inserted and the resulting STS sig nal is transmitted in byte wide format to a parallel to serial converter and then to a fiber optic transceiver In th...

Page 25: ...s Monitors the M1 byte to determine the number of B2 errors that are detected by the remote terminal in its received signal Outputs the received E1 F1 and E2 bytes and two serial DCC channels SDCC D1...

Page 26: ...de for insertion into the transmit path status byte G1 as a Remote Error Indication If regis ter bit PREI_INH 0 the bits are set to the binary value 0000 through 1000 indicating between 0 and 8 equal...

Page 27: ...e served bytes for STM 1 3 9 3 3 1 TOH SOH AIS Generation Normal generation of TOH SOH bytes is suspended during trans mission of LAIS or PAIS If TX_LAIS 1 the first three rows of the TOH SOH are gene...

Page 28: ...The re ceived E1 E2 and F1 bytes will be inserted into the outgoing SONET SDH frame which follows the reception of the last bit of the E1 E2 and F1 bytes 3 9 3 3 7 Data Communications Chan nels DCC D...

Page 29: ...ted five MSBs of K2 bytes The three LSBs of K2 are con trolled from three sources In order of priority these are if TX_LAIS 1 the bits are transmitted as all ones as are all line MS overhead bytes ind...

Page 30: ...ved with at least one MSB bit error In SONET mode the J0 frame indication is held in the in frame state J0_OOF 0 The J0_OOF_D delta bit is set when J0_OOF changes state 3 9 4 2 3 Pattern Acceptance an...

Page 31: ...the performance monitoring counters are latched the value of this counter is latched to the M1_ERRCNT 23 0 register and the M1 error counter is cleared 3 9 4 3 Transport Overhead Drop The TOH SOH dro...

Page 32: ...ointer with its D bits inverted a negative justification is indicated The H3 byte is considered a negative stuff byte it is part of the SPE and the current accepted pointer value is decremented by 1 m...

Page 33: ...ise if the AIS or AISC states are entered the corre sponding HPAIS interrupt request bit will be set 3 9 4 9 Path Overhead Monitoring The POH monitoring block con sists of J1 B3 C2 and G1 monitoring T...

Page 34: ..._AVL event bit 3 9 4 9 3 16 Byte J1 Monitoring In SDH mode the J1 bytes are ex pected to contain a repeating 16 byte path trace frame that in cludes the PAPI In this mode the J1_READ J1_MODE and J1_AV...

Page 35: ...ted by G1 When the performance monitoring counters are latched LATCH_EVENT tran sitions high the value of this counter is latched to the G1_ERRCNT 15 0 register and the G1 error counter is cleared 3 9...

Page 36: ...RMR_INH 1 an external framer must supply the HDMP 3001 with a start of frame indication RX_FRAME_IN The HDMP 3001 sets its internal frame counter when the RX_FRAME_IN input transitions from 0 to 1 The...

Page 37: ...lue is then compared to the re ceived B1 value in the following frame after descrambling The comparison can result in 0 to 8 mismatches B1 bit errors The HDMP 3001 contains a 16 bit B1 error counter t...

Page 38: ...de both MII clocks are inputs so there is no risk of having enabled opposing drivers The mode is se lected by writing to an internal register which should only be done after reset and then remain cons...

Page 39: ...ways 0 Interrupt output INT is asserted with 0 and de asserted with 1 Enabled externally Output buffer OEN is always driven to 0 Output buffer s Active 0 input pin is driven by an inversion of the int...

Page 40: ...01 mapped to the smallest memory bank 32 Kbytes BR 20 31 010000000001 which sets no parity 8 bits data GPCM controlled OR 20 31 000100001000 which sets normal CS timing no burst allowed externally gen...

Page 41: ...1 Configuration 1 HDMP 3001 is set up through the microprocessor or MII Manage ment ports No EEPROM needed Connect SCL and SDA to ground Disable SCL and SDA pull ups to save power 4 3 4 2 Configurati...

Page 42: ...ess Bit Type Bit Name Default value Description 0 15 R W Reset 0 Reset PHY This bit clears automatically when reset is complete 14 R W Loopback 0 Loopback on off Default off 13 R Speed Selection LSB F...

Page 43: ...Unique Identifier 3 15 10 R PHY Identifier Fixed 010011 Bits 19 to 24 of the IEEE assigned Organizationally Unique Identifier 9 4 Fixed 000010 Manufacturer s Model Number 3 0 Fixed 0000 Revision Numb...

Page 44: ...ask 0x00B SONET SDH Configuration 0x00C Reserved 0x00D GPIO Control 0x00E 0x00F GPIO Data 0x010 0x09B Reserved SONET SDH Transmit Registers 0x09C Transmit BIP Control 0x09D Transmit AIS RDI REI Contro...

Page 45: ...FB Reserved 0x0FC Receive LOH Monitor Masks 0x0FD Receive SOH Monitor Masks 0x0FE Reserved 0x0FF Receive TOH Monitor Control 1 0x100 Reserved 0x101 Receive Framer Position Control 0x102 Receive LOH St...

Page 46: ...2E Receive J1 Mode Control 0x12F Receive RDI Monitor 0x130 Receive J1 Delta 0x131 Receive J1 Mask 0x132 Receive POH Mask 0x133 Receive J1 OOF 0x134 0x173 Receive J1 Bytes 64 0x174 Receive Path Delta 0...

Page 47: ...er 0x198 0x19B Transmit FIFO Overflow Error 0x19C 0x19F Transmit FIFO Underrun Error 0x1A0 Ethernet Transmit Interrupt Event 0x1A1 Ethernet Transmit Interrupt Mask 0x1A2 0x1BF Reserved Ethernet Receiv...

Page 48: ...um Frame Size Violations 0x1F8 0x1FB Receive Maximum Frame Size Violations 0x1FC 0x1FF Reserved In the register definition tables in the following sections NAMES of the registers are specified in abbr...

Page 49: ...ET_R_ SONET_R_ T_TO_R_ TO_T_LOOP TO_T_ LOOP LOOPL R W R W R W R W Value 0 0 0 0 0 0 0 0 after reset ADDR 0x001 Test Modes Bits 7 3 Reserved Bit 2 MII_T_TO_R_LOOP is set to enable MII loopback mode to...

Page 50: ...tive level 1 Refer to Section 4 2 4 Interrupt Modes of HDMP 3001 P Interrupt Output for more information ADDR 0x003 Microprocessor Interrupt Pin Mode 1 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit...

Page 51: ...2 Bit 1 Bit 0 Bit name Reserved Reserved Reserved Reserved Reserved Reserved RX_APS_ SUM_INT INT R W R R Value 0 0 0 0 0 0 0 0 after reset ADDR 0x006 Interrupt Status Bits 7 2 Reserved Bit 1 RX_APS_I...

Page 52: ...ta signals NEW_RX_OOS_ERR NEW_RX_FORM_DEST_ERR NEW_RX_FIFO_UR_ERR NEW_RX_FIFO_OF_ERR NEW_RX_FCS_HEC_ERR NEW_TX_FIFO_UR_ERR NEW_TX_FIFO_OF_ERR NEW_TX_ER_ERR NEW_TX_MII_ALIGN_ERR is set and enabled Bits...

Page 53: ...in address 0 bit 10 Bit 2 SONET SDH 0 in SONET mode 1 in SDH mode Bit 1 PHY MAC 0 in MAC mode 1 in PHY mode Bit 0 GFP LAPS 0 in LAPS mode 1 in GFP mode ADDR 0x00A Rx Event Summary Mask Bit 7 Bit 6 Bi...

Page 54: ...er reset ADDR 0x00D GPIO Control Bit 7 GPIOCTL7 If 0 GPIO15 and GPIO14 are configured as inputs If 1 GPIO15 and GPIO14 are configured as outputs Bit 6 GPIOCTL6 If 0 GPIO13 and GPIO12 are configured as...

Page 55: ...0E GPIO 7 0 Data Bits 7 0 GPIO 7 0 General purpose I O bits 7 0 and they are defaulted as inputs Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO...

Page 56: ...B1_INV TX_B2_INV TX_B3_INV R W R W R W R W Value 0 0 0 0 0 0 0 0 after reset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name TX_LAIS Reserved Reserved Reserved Reserved Reserved LRDI_INH LREI...

Page 57: ...Bit 1 Bit 0 Bit name TEST_K2 7 0 R W R W Value 0 0 0 0 0 0 0 0 after reset ADDR 0x0B0 Transmit K2 Byte TX_K2 7 3 These bits are automatic protection switching APS signaling TX_K2 2 0 These bits are c...

Page 58: ...1 7 0 The transmitted S1 byte of the HDMP 3001 is set equal to TX_S1 7 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name Reserved Reserved Reserved Reserved Reserved PREI_INH PRDI_ENH PRDI_AU...

Page 59: ...ONET SDH 1 the J1 byte is transmitted repetitively as the 16 byte sequence in TX_J1 15 _ 7 0 down to TX_J1 0 _ 7 0 2 When SONET SDH 0 the J1 byte is transmitted repetitively as the 64 byte sequence in...

Page 60: ...ree bits Bits 3 1 Reserved Bit 0 TX_PAIS If 1 the TOH SOH is normally generated except that the pointer bytes H1 H2 and H3 in row 4 as well as all SPE VC bytes are transmitted as all ones If 0 the pay...

Page 61: ...Bit 0 Bit name J0_OOF Reserved RX_LAIS RX_LRDI RX_K1_D K1_UNSTAB RX_K2_D Reserved _D _D _D _D R W W1C W1C W1C W1C W1C W1C Value 0 0 0 0 0 0 0 0 after reset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 B...

Page 62: ...Bit 0 Reserved always write as one These bits are used to enable disable reporting status of the corresponding event bits If set reporting status of the corresponding event bits is disabled Bit 7 Bit...

Page 63: ...1 the HDMP 3001 receive framer is enable and the parallel input signal is not assumed to be byte aligned If 0 the receive framer in the HDMP 3001 is bypassed and it requires a frame start condition R...

Page 64: ...he three LSBs of the received K2 byte are not received as 111 for the number of consecutive frames specified in the K2_CONSEC_NUM 3 0 Bit 4 RX_LRDI It will be asserted after the three LSBs of the rece...

Page 65: ...l indication from the optical transceiver Bit 4 Reserved Bit 3 RX_OOF RX_OOF 1 if the receive framer receives five successive frames with at least one bit error in the A1 A2 A2 A2 framing pattern RX_O...

Page 66: ...it 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name Reserved Reserved Reserved Reserved RX_S1 3 0 R W R Value 0 0 0 0 0 0 0 0 after reset ADDR 0x114 Receive S1 LSBs Bits 7 4 Reserved Bits 3 0 RX_S1 3 0 Synchronizat...

Page 67: ...Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name B1_ERRCNT 7 0 R W R Value 0 0 0 0 0 0 0 0 after reset ADDR 0x118 Receive B1 Error Count Bits 7 0 B1_ERRCNT 7 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 B...

Page 68: ...ERRCNT 7 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name B2_ERRCNT 15 8 R W R Value 0 0 0 0 0 0 0 0 after reset ADDR 0x11C Receive B2 Error Count Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 B...

Page 69: ...Error Count Bits 7 0 M1_ERRCNT 15 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name M1_ERRCNT 23 16 R W R Value 0 0 0 0 0 0 0 0 after reset ADDR 0x121 Receive M1 Error Count Bits 7 0 M1_ERRCN...

Page 70: ...disable status reporting of the corresponding event bits If set the reporting status of the corresponding bit in the event register is disabled ADDR 0x126 Receive Pointer Interpreter Delta Bit 7 Bit 6...

Page 71: ...R R R Value 0 0 0 1 0 1 0 0 after reset ADDR 0x12A Receive Pointer Status 2 Bits 7 6 Reserved Bit 5 LOP3 It is used to monitor the third pair of H1 H2 pointer bytes for the correct concatenation indic...

Page 72: ...its 6 0 Reserved Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name Reserved Reserved Reserved Reserved Reserved Reserved J1_MODE Reserved R W R W Value 0 0 0 0 0 0 0 0 after reset ADDR 0x12E Re...

Page 73: ...rmine which bits of the G1 byte will be monitored for Path RDI indication If set the HDMP 3001 will use only bit 5 of the received G1 byte If not bits 5 6 and 7 of the received G1 byte will be used Bi...

Page 74: ...corresponding event bits is disabled Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name Reserved Reserved Reserved RX_C2_D_ RX_G1_D_ RX_UNEQ_ RX_PLM_D Reserved MASK MASK D_MASK _MASK R W R W R...

Page 75: ...h a one in its MSB When J1_OOF 0 it indicates this pattern is found the framer goes into frame When J1_OOF 1 it indicates this pattern match is lost three consecutive J1 bytes with MSB errors Bit 7 Bi...

Page 76: ...0 R W R W Value 0 0 0 1 1 0 0 0 after reset ADDR 0x176 Expected C2 Byte Bits 7 0 EXP_C2 7 0 The received C2 bytes are monitored so that reception of the correct type of payload can be verified When a...

Page 77: ...Bit 1 RX_PLM It contributes to the insertion of Path RDI Bit 0 Reserved Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name EXP_C2 7 0 R W R W Value 0 0 0 1 1 0 0 0 after reset ADDR 0x179 Receiv...

Page 78: ...P 8 B3 error Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name G1_ERRCNT 7 0 R W R Value 0x00 after reset ADDR 0x17E G1 Error Count Bits 7 0 G1_ERRCNT 7 0 The lower byte of the G1 error counter...

Page 79: ...ted FCS fields to be sent Bit 0 TX_FCS_INH is set to inhibit the TX FCS 32 bit CRC field from being transmitted Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name TX_ADR_DPSP 7 0 R W R W Value 0...

Page 80: ...3 Bit 2 Bit 1 Bit 0 Bit name TX_RA_TYPE_H 7 0 R W R W Value 0xDD after reset ADDR 0x183 Transmit Rate Adaptation Type_H Byte Bits 7 0 TX_RA_TYPE_H 7 0 specifies the Rate Adaptation Byte for LAPS mode...

Page 81: ...read data out of the TX FIFO when the number of bytes of the portion of the transmitting frame that has been stored into the TX FIFO is equal to or greater than the programmed TX_FIFO_THRESHOLD The d...

Page 82: ...ation sequence when an underrun occurs in the TX FIFO If the abort sequence is also inhibited the FCS is corrupted ADDR 0x187 Transmit GFP Mode Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name...

Page 83: ...e field byte in GFP frame In LAPS mode it is sent as part of the header unless the TX_SAPI_INH bit is set In GFP mode it is part of the extended header and is sent if TX_EXT_HDR_INH is not set Bit 7 B...

Page 84: ...7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name 0x18C TX_MII_FRAMES_REC_OK 7 0 0x18D TX_MII_FRAMES_REC_OK 15 8 0x18E TX_MII_FRAMES_REC_OK 23 16 0x18F Fixed 0 R W RO Value 0 after reset ADDR 0x19...

Page 85: ...ted by frames where TX_ER was detected active while the frame was being received but did not cause a FIFO error ADDR 0x198 0x19B TX FIFO Overflow Error ADDR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 B...

Page 86: ...RR R W R W R W R W R W W1C W1C W1C W1C Value 0 0 0 0 0 0 0 0 after reset Bits 7 4 Reserved Bit 3 NEW_TX_FIFO_UR_ERR is set whenever a new TX FIFO Underrun Error occurs and is cleared when a 1 is writt...

Page 87: ...es not affect the corresponding interrupt event bit Bit 2 NEW_TX_FIFO_OF_MASK is set to suppress the new TX FIFO Overflow Error from setting the EoS_D_SUM Summary Interrupt bit This interrupt mask bit...

Page 88: ...Bit 0 Bit name Reserved Reserved Reserved Reserved Reserved RX_DES_ RX_FCS_ RX_FCS_ INH INH REM_INH R W R W R W R W Value 0 0 0 0 0 0 0 0 after reset Bits 7 0 RX_FIFO_THRESHOLD 7 0 is the LSB of the...

Page 89: ...G_SEL for the MII RX interface from Normal IFG to Low IFG The IFG Selection Mode is used to control the minimum number of MII clock cycles between consecutive MAC frames sent out on the MII RX bus fro...

Page 90: ...G_SEL for the MII RX interface from Low IFG to Normal IFG The IFG Selection Mode is used to control the minimum number of MII clock cycles between consecutive MAC frames sent out on the MII RX bus fro...

Page 91: ...Reserved Bits 4 0 NORMAL_IFG 4 0 specifies the Normal Inter Frame Gap which is used by the MII RX interface to insert the minimum number of idle cycles between two MAC frames sent out onto the MII RX...

Page 92: ...Inter Frame Gap Water Mark IFG_SEL is set to zero for Normal IFG At power up IFG_SEL defaults to zero for Normal IFG selection This value remains zero until the number of bytes in the RX FIFO becomes...

Page 93: ...ECK_INH is not set The default value is assigned to 0x03 for LAPS since LAPS is the default mode For GFP mode this register must be programmed to 0x10 for Null Headers with FCS Bit 7 Bit 6 Bit 5 Bit 4...

Page 94: ...MII interface Bit 4 RX_CNT_REM_INH is set to inhibit the removal of the received Control field When set the Control field is prepended to the MAC Payload When cleared the Control field is not forward...

Page 95: ...forwarded through the MII interface Bits 5 RX_EHEC_CHECK_INH is set to inhibit the checking of the received eHEC field Bits 4 RX_THEC_CHECK_INH is set to inhibit the checking of the received tHEC fie...

Page 96: ...ks frame by frame for a correct cHEC The process repeats until RX_PRESYNC consecutive correct HECs are confirmed at which point the process moves to the Sync state If an incorrect cHEC is found the pr...

Page 97: ...serted That is it is incremented by each frame that did not increment any one of the error counters ADDR 0x1D8 B Receive FCS and HEC Error Counter ADDR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0...

Page 98: ...counters and In GFP mode an error is found in the Type DP SP or Spare fields and checking of the corresponding field is enabled In LAPS mode an error is found in the Address Control or SAPI fields and...

Page 99: ...o again This counter is incremented each time there is a FIFO overflow and hence a frame is discarded ADDR 0x1E8 EB Receive FIFO Underrun Error ADDR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit...

Page 100: ...t of Sync Error occurs and cleared when a one is written to this bit For more information refer to the register definition of RX Out of Sync Error counter Bit 3 NEW_RX_FORM_DEST_ERR is set whenever a...

Page 101: ...bit does not affect the corresponding interrupt event bit Bit 2 NEW_RX_FIFO_UR_MASK is set to suppress the new RX FIFO Underrun Error from setting the EOS_D_SUM Summary Interrupt bit This interrupt ma...

Page 102: ...Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name RX_MAX_SIZE 7 0 R W R W Value 0xF2 after reset ADDR 0x1F0 Receive Maximum Frame Size LSB Bits 7 0 RX_MAX_SIZE specifies the maximum Ethernet fr...

Page 103: ...FO_UR_ERR or RX_FIFO_OF_ERR counters but contained fewer than RX_MIN_SIZE bytes and checking was turned on ADDR 0x1F8 B Receive Maximum Frame Size Violations 15 0 ADDR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bi...

Page 104: ...LLLLL NNN G YYWW R R CCCCC LLLLLLLLL WAFER LOT NUMBER NNN WAFER NUMBER G SUPPLIER CODE YY LAST TWO DIGITS OF YEAR WW TWO DIGIT WORK WEEK R R DIE REVISION NUMBER CCCCC COUNTRY OF ORIGIN Figure 24 Packa...

Page 105: ...m PER SIDE D1 AND E1 ARE MAXIMUM PLASTIC BODY SIZE DIMENSIONS INCLUDING MOLD MISMATCH DIMENSIONS D1 AND E1 SHALL BE DETERMINED AT DATUM PLANE H 6 DETAILS OF PIN 1 IDENTIFIER ARE OPTIONAL BUT MUST BE L...

Page 106: ...D 31 20 Bsc 4 D1 28 00 Bsc Package length D2 25 35 Bsc E 31 20 Bsc E1 28 00 Bsc Package width E2 25 35 Bsc L 0 73 0 88 1 03 N 160 Lead count e 0 65 Bsc Lead pitch b 0 22 0 40 Plated lead width b1 0 2...

Page 107: ...ating Conditions Parameter Min Typ Max Units Supply Voltage DVDD 2 97 3 3 3 63 Volts Supply Voltage VDD 1 62 1 8 1 98 Volts Case Temperature 0 25 85 C 7 3 Thermal Characteristics Table 25 Thermal Perf...

Page 108: ...ty Cycle 35 65 Time 40 ns Output Rise Time 0 65 5 ns Load 15 pF from 30 70 1 2 V Output Fall Time 0 65 5 ns Load 15 pF from 30 70 1 2 V HiZ Leakage Current 10 10 A 7 4 DC Characteristics The specifica...

Page 109: ...M_TXD P_RX_DV_M_TX_EN P_RX_ER_M_TX_ER P_RX_CLK_M_TX_CLK MAC mode output hold time 0 ns P_RXD_M_TXD P_RX_DV_M_TX_EN P_RX_ER_M_TX_ER P_RX_CLK_M_TX_CLK PHY mode Input Setup time 15 ns P_TXD_M_RXD P_TX_DV...

Page 110: ...Timing RDYB is re clocked twice by the microprocessor clock in addition to the timing shown This adds an additional delay of between one and two microprocessor clock cycles VALID VALID NEW VALUE t1 t2...

Page 111: ...ocked twice by the microprocessor clock in addition to the timing shown This adds an additional delay of between one and two microprocessor clock cycles VALID t7 t10 t9 INVALID VALID CAPTURED Hi Z Hi...

Page 112: ...the 300 520 GPIOs are the target of the read cycle t9 CS_N WRB and RDB valid to D valid 600 750 t10 1 D valid to RDYB active 50 1 60 1 t11 CS_N WRB and RDB valid to RDYB active 650 850 t12 RDB inacti...

Page 113: ...g TX_E1E2F1_CLK TX_E1_DATA TX_E2_DATA TX_F1_DATA tHE1FC tSE1TC tHE2FC tSE2TC tHF1FC tSF1TC Label Parameter Min Typ Max Units TX_E1E2F1_CLK TX_E1E2F1_CLK frequency 64 kHz tSE1TC Setup TX_E1_DATA to TX_...

Page 114: ...F1_CLK low 30 70 ns 8 7 DCC Interface Transmit Timing TX_SDCC_CLK TX_LDCC_CLK TX_SDCC_DATA TX_LDCC_DATA tSSDCTC tHSDFC tSLDCTC tHLDFC Label Parameter Min Typ Max Units TX_SDCC_CLK TX_SDCC_CLK frequenc...

Page 115: ...FC Transition RX_LDCC_DATA from RX_LDCC_CLK 30 70 ns 8 9 JTAG Interface Timing TCK TDI TMS TDO tHTDO tSTDI tHTD1 tSTMS tHTMS Label Parameter Min Typ Max Units TCK TCK frequency 10 MHz tSTDI Setup TDI...

Page 116: ...ast 200 SONET clock cycles 10 s with stable power TX_CLK TX_D 3 0 TX_EN TX_ER RX_D 3 0 RX_DV RX_ER RX_CLK tTX 0 ns MIN 25 ns MAX tRXS 10 ns MIN tRXH 10 ns MIN VALID VALID Figure 38 MII timing as defin...

Page 117: ...M_TX_CLK P_RX_ER M_TX_ER Max 25 ns round trip delay P_RX_CLK M_TX_CLK In RX P_TXD 3 0 M_RXD 3 0 In Clocked in by P_TX_EN M_RX_DV P_TX_CLK M_RX_CLK P_TX_ER M_RX_ER P_TX_CLK M_RX_CLK P_TX_CLK M_RX_CLK I...

Page 118: ...hold time does not have to be met if the slave device stretches the low period of SCL 8 14 In Frame Declaration RX_DATA 7 0 RX_SONETCLK RX_FRAME_IN OOF 125 s BETWEEN FRAMING PATTERN OCCURRENCES A1 A1...

Page 119: ...ation Removal The loss of frame declaration removal timing diagram Figure 41 illustrates the operation of the LOF output LOF is an integrated version of OOF LOF is declared when an out of frame condit...

Page 120: ...nship between the TX_E1_DATA TX_E2_DATA and TX_F1_DATA serial data inputs and their associated clock TX_E1E2F1_CLK It is a 72 kHz 50 duty cycle clock that is gapped to produce a 64 kHz nominal rate an...

Page 121: ...d Data Alignment The receive overhead alignment timing diagram Figure 44 shows the relationship between the RX_E1_DATA RX_E2_DATA and RX_F1_DATA serial data outputs and their associated clock RX_E1E2F...

Page 122: ...d Data Alignment The transmit data link clock and data alignment timing diagram Figure 45 shows the relationship between the TX_SDCC_DATA and TX_LDCC_DATA serial data inputs and their associated clock...

Page 123: ...and Data Alignment The receive data link clock and data alignment timing diagram Figure 46 shows the relationship between the RX_SDCC_DATA and RX_LDCC_DATA serial data outputs and their associated cl...

Page 124: ...eneric Framing Procedure GFP Draft Revision 3 Enrique Hernandez Valencia 2 ITU T Recommendation X 86 3 IEEE Std 802 3 2000 Edition 4 ANSI Digital Hierarchy Optical Interface Rates and Format Specifica...

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