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SOM-9590 User Manual
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Feature
Options
Description
Hyper-Threading [ALL]
Enable
Disable
Enable Hyper Threading (software
method to enable/disable logical
processor threads).
Monitor/Mwait
Enable
Disable
Enable or disable the Monitor/Mwait
instruction.
Execute Disable Bit
Enable
Disable
When disabled, forces the XD fea
-
ture flag to always return to 0.
Enable Intel TXT Support Enable
Disable
Enable Intel Trusted Execution
Technology Configuration. Please
disable “EVDFX Features” when
TXT is enabled.
VMX
Enable
Disable
Enable Vanderpool Technology,
takes effect after reboot.
Enable SMX
Enable
Disable
Enable Safe Mode Extensions.
Lock Chipset
Enable
Disable
Lock or unlock chipset.
MSR Lock Control
Enable
Disable
Enable-MSR 3Ah, MSR 0E2h and
CSR 80h will locked. Power good
reset is needed to remove locked
bits.
PPIN Control
Unlock/Enable
Unlock/Disable
Unlock and enable/disable PPIN
Control.
Debug Interface
Enable
Disable
MSR 0C80h bit [0], enables debug
-
ging features when set.
Hardware Prefetcher
Enable
Disable
MLC Streamer Prefetcher (MSR
1A4h Bit[0]).
Feature
Options
Description
Adjacent Cache
Prefetcher
Enable
Disable
MLC Spatial Prefetcher (MSR 1A4h
Bit[1]).
DCU Streamer
Prefetcher
Enable
Disable
DCU streamer prefetcher is an L1
data cache prefetcher (MSR 1A4h
[2]).
DCU IP Prefetcher
Enable
Disable
DCU IP prefetcher is an L1 data
cache prefetcher (MSR 1A4h [3]).
DCU Mode
32KB 8Way Without ECC
16KB 4Way Without ECC
MSR 31h Bit [0] -A write of 1 selects
the DCU mode as 16KB 4-way with
ECC.
Direct Cache Access
(DCA)
Auto
Enable
Disable
Enables Direct Cache Access.
Summary of Contents for SOM-9590
Page 94: ...SOM 9590 User Manual 86...
Page 98: ...SOM 9590 User Manual 90...
Page 105: ...97 SOM 9590 User Manual Appendix A Pin Assignment...