RSB-4410 User Manual
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u32 xres;
u32 yres;
u32 pixclock;
u32 left_margin;
u32 right_margin;
u32 upper_margin;
u32 lower_margin;
u32 hsync_len;
u32 vsync_len;
u32 sync;
u32 vmode;
u32 flag;
};
3.8.4.2
Single Display Settings
HDMI out, please set in u-boot as below:
setenv bootargs_mmc 'setenv bootargs ${bootargs} root=/dev/
mmcblk1p1 rootwait rw video=mxcfb0:dev=hdmi,1920x1080M
@60,if=RGB24’
VGA out, please set in u-boot as below:
setenv bootargs_mmc 'setenv bootargs ${bootargs} root=/dev/
mmcblk1p1 rootwait rw video=mxcfb0:dev=lcd,1920x1080M
@60,if=RGB24’
LVDS (Single) out, please set in u-boot as below:
setenv bootargs_mmc 'setenv bootargs ${bootargs} root=/dev/
mmcblk1p1 rootwait rw video=mxcfb0:dev=ldb,1920x1080M
@60,if=RGB24’
3.8.4.3
Multi Display Settings
When you want to display dual LVDS, VGA and HDMI output , please set parameter
in U-boot as following. This is the default settings in U-boot.
setenv bootargs_mmc 'setenv bootargs ${bootargs} root=/dev/
mmcblk1p1 rootwait
setenv bootargs_base ‘setenv bootargs console=ttymxc0,
115200 enable_wait_mode=off video_mode=extension’
For display interface clock, there are several options (Independently for each port)
listed below:
1.
Derived from the IPU internal clock (Master Mode)
2.
Provided by an external source (Slave Mode)
3.
The transfer rate supported
When a single port is active, the pixel clock rate is up to 264 MHz
When both LVDS ports are active, you have to follow below condition:
1) Each pixel clock rate may be up to 220 MHz**
