Advantech POD-6552 A2, User Manual

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25 POD-6552 A2 User Manual
Chapter 3
B
IOS Operation
3.2.4 Advanced Chipset Features
DRAM Timing Selectable [By SPD]
This item allows the user to set optimal timings for items 2 through 5. The sys-
tem default setting of “By SPD” follows the SPD information on the ROM chip
and ensures the system runs stably, with optimal performance.
CAS Latency Time [2.5]
This item allows the user to set the timing delay in clock cycles before SDRAM
starts a read command after receiving it.
DRAM RAS# to CAS# Delay [3]
This item allows the user to set the timing of the transition from RAS (row
address strobe) to CAS (column address strobe) as both rows and columns are
separately addressed shortly after the DRAM is refreshed.
DRAM RAS# Precharge [3]
This item allows the user to set the DRAM RAS# precharge timing. The system
default is set to “Auto” to reference the data from the SPD ROM.
Active to Precharge Delay [7]
This item allows the user to adjust memory precharge time.
MGM Core Frequency [Auto Max 266 Mhz]
This item enables users to set the operation speed of internal Graphic Chip
FSB and DRAM , system default is setting to “Auto Max 266 MHz” to reference
value..
System BIOS Cacheable [Enabled]
This item allows the system BIOS to be cached to allow faster execution and
better performance.
Video BIOS Cacheable [Disabled]
This item allows the video BIOS to be cached to allow faster execution and bet-
ter performance.
Note! The "Advanced Chipset Features" screen controls the configuration of
the board's chipset register settings and performance tuning - the
options on this screen may vary depending on the chipset type. It is
strongly recommended that only technical users make changes to the
default settings.