Advantech PCLS-848-P, User Manual

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CHAPTER 2 INSTALLATION 9
2.2.4. DMALevel Setting
The PCL-848A/B is designed to permit DMA(Direct Memory Access) data transfer
between IEEE-488 bus and the system RAM of the PC. The DMAlevel is set by JP1
and JP2. The JP1 is for DACK signal 3! path while the JP2 is for DRQ. The settrugs
of JP1 and JP2 must be coincident. For example, if the JP1 is set to DACK3, then JP2
must be set to DRQ 3.
2.2.5. Interrupt Level (IRQ) Setting
The PCL-848A/B is designed to permit access to interrupt level 2 up to level 7 and
the interrupt is initiated by the NEC7210 GP interface controller. The selection is
made by setting JP3.
Note: Although the IRQ level can be set from IRQ 2 to IRQ 7 on the
board, the firmware supports IRQ 2, 3, 5, and 7 only.
2.3. Installmg the Card 2.3.1. Preparation
Discharge any static electricity by touching the back of the system s~ unit before you
handle the board. You should avoid contact with e)3 materials that create static
electricity such as plastic, vinyl, and styrofoam.
The IEEE-488 interface card is setup at the factory of default setting: