Advantech PCL-730, User Manual

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vii PCL-730 User Manual
Contents
Chapter 1 Overview ...............................................1
1.1 Introduction ............................................................................................... 2
1.2 Features .................................................................................................... 2
1.3 Applications............................................................................................... 2
1.4 Specifications ............................................................................................ 3
1.5 Daughterboards ........................................................................................ 4
Chapter 2 Hardware Installation ..........................5
2.1 Installation ................................................................................................. 6
2.2 Initial Inspection ........................................................................................ 6
2.3 Switch and Jumper Settings...................................................................... 7
Table 2.1: Connectors, Jumpers, and Switches .......................... 7
2.4 Base Address selection (SW1) ................................................................. 8
2.4.1
Interrupt level (JP1)....................................................................... 8
2.4.2 Interrupt triggering (JP2) ............................................................... 9
2.4.3 Interrupt source (JP3) ................................................................... 9
2.4.4 Version control (JP4/JP5) ............................................................. 9
2.5 Hardware Installation ............................................................................. 10
Chapter 3 Signal Connections ...........................11
3.1 Overview ................................................................................................. 12
3.2 Connector Pin Assignments.................................................................... 12
3.3 TTL-level I/O ........................................................................................... 14
3.3.1
Isolated Input .............................................................................. 14
3.3.2 Isolated Output............................................................................ 15
Appendix A Register Format .................................17
A.1 Register Format ...................................................................................... 18
Table A.1: Register Assignment ................................................ 18
Appendix B PC I/O Port Address Map ..................19
B.1 PC I/O port address map ........................................................................ 20