Advantech PCIE-1750U, User Manual

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vii PCIE-1750U/UH User Manual
Contents
Chapter 1 Overview ...............................................1
1.1 Introduction ............................................................................................... 2
1.2 Features .................................................................................................... 2
1.3 Applications............................................................................................... 3
1.4 Installation Guide ...................................................................................... 3
1.5 Software Overview .................................................................................... 4
1.6 Accessories............................................................................................... 4
1.7 Ordering Information: ................................................................................ 4
Chapter 2 Hardware Installation ..........................5
2.1 Installation ................................................................................................. 6
2.2 Unpacking ................................................................................................. 6
2.3 Driver Installation ...................................................................................... 7
2.4 Hardware Installation ................................................................................ 7
Figure 2.1 Device Manager ......................................................... 8
Chapter 3 Signal Connections .............................9
3.1 Overview ................................................................................................. 10
3.2 Switch and Jumper Settings.................................................................... 10
Figure 3.1 Card layout of PCIE-1750U/UH................................ 10
Table 3.1: Summary of Jumper Settings (JP2).......................... 10
Table 3.2: Board ID setting (SW1)............................................. 11
3.3 Signal Connections ................................................................................. 12
Figure 3.2 Pin assignment of PCIE-1750U/UH......................... 12
Figure 3.3 Isolated DI Connection ............................................. 13
Figure 3.4 Sink type (NPN) connection ..................................... 13
Figure 3.5 Source type (PNP) connection ................................. 14
Figure 3.6 Wrong connection wouldn’t damage the IDO compo-
nent........................................................................... 14
Figure 3.7 Pin definition of CN2................................................. 15
Appendix A Specifications ....................................17
A.1 Specifications .......................................................................................... 18
A.1.1 Isolated Digital Input ................................................................... 18
A.1.2 Isolated Digital Output................................................................. 18
A.1.3 General ....................................................................................... 19
A.1.4 Digital Filter Time ........................................................................ 19
Appendix B Block Diagram ...................................21
B.1 PCIE-1750U/UH...................................................................................... 22