Advantech PCI-7020, User Manual

Page: 18 / 90

PCI-7020 User Manual 8
1.8.3 Watchdog Timer Output (JWDT1)
The PCI-7020 contains a watchdog timer that will reset the CPU in the event the CPU
stops processing. This feature means the PCI-7020 will recover from a soft- ware fail-
ure or an EMI problem. The JWDT1 jumper settings control the outcome of what the
computer will do in the event the watchdog timer is tripped.
1.9 System Memory
The PCI-7020 has two sockets for 200-pin dual inline memory modules (SODIMMs)
in two memory channels. All these sockets use 1.8 V unbuffered double data rate
synchronous DRAMs (DDR2 SDRAM). They are available in capacities of 256, 512,
1024 and 2048 MB. The sockets can be filled in any combination with DIMMs of any
size, giving a total memory size between 256 MB and 4 GB.
1.9.1 CPU FSB and Memory Speed
The PCI-7020 supports Intel LGA775 CPUs with FSB 533/800/1066. The PCI-7020
can accept DDR2 SDRAM memory chips without parity. Also note: The PCI-7020
accepts DDR2 533/667MHz SDRAM. The PCI-7020 does NOT support ECC (error
checking and correction).
1.10 Memory Installation Procedures
To install DIMMs, slowly slide the DIMM module along the plastic guides on both
ends of the socket. Then press the DIMM module right down into the socket, until you
hear a click. This is when the two handles have automatically locked the memory
module into the correct position of the DIMM socket.
Table 1.3: CMOS (CMOS1)
Function Jumper Setting
Keep CMOS data *
1-2 closed
Clear CMOS data
2-3 closed
*default setting
1
1
Table 1.4: Watchdog Timer Output (JWDT1)
Function Jumper Setting
NC
1-2 closed
Reset*
2-3 closed
*default setting
1
1