Advantech PCI-1751, User Manual

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PCI-1751 User Manual 12
3.3 Pin Assignments
Description of pin use:
PA00 ~ PA07: I/O pins of Port A0
PA10 ~ PA17: I/O pins of Port A1
PB00 ~ PB07: I/O pins of Port B0
PB10 ~ PB17: I/O pins of Port B1
PC00 ~ PC07: I/O pins of Port C0
PC10 ~ PC17: I/O pins of Port C1
CNT0_OUT, CNT1_OUT and CNT2_OUT:
Output pins of Counter/Timer 0, 1 and 2
CNT0_CLK, CNT1_CLK and CNT2_CLK:
External clock source of Counter / Timer 0, 1 and 2
CNT0_G, CNT1_G and CNT2_G:
Gate control pins of Counter / Timer 0, 1 and 2
INT_OUT: Interrupt output. This pin changes to logic 1
whenever the PCI-1751 generates an interrupt, and
returns to logic 0 when the interrupt is cleared.
GND: Ground
VCC: +5 VDC voltage output
Table 3.2: Board ID setting (SW1)
ID3 ID2 ID1 ID0 Board ID
1 1 1 1 0
1 1 1 0 1
1 1 0 1 2
1 1 0 0 3
1 0 1 1 4
1 0 1 0 5
1 0 0 1 6
1 0 0 0 7
0 1 1 1 8
0 1 1 0 9
0 1 0 1 10
0 1 0 0 11
0 0 1 1 12
0 0 1 0 13
0 0 0 1 14
0 0 0 0 15
Note!
On: 1, Off: 0