Advantech MIC-3612/3-BE, User Manual

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21 MIC-3612/3-BE User Manual
Chapter 4
R
egister
Structure
BASE+4 Modem Control Register (MCR)
Bit 0 DTR
Bit 1 RTS
Bit 2 OP1# Output/Auto RS485 Control
Bit 3 OP2# or IRQn Enable during PC Mode
Bit 4 Internal Loopback Enable
Bit 5 Xon-Any Enable
Bit 6 Infrared Encoder/Decoder Enable
Bit 7 Clock prescale select
BASE+5 Line Status Register (LSR)
Bit 0 Receiver data ready
Bit 1 Overrun error
Bit 2 Parity error
Bit 3 Framing error
Bit 4 Break interrupt
Bit 5 Transmitter holding register empty
Bit 6 Transmitter shift register empty
Bit 7 At least one parity error, framing error or break indication in the FIFO
BASE+6 Modem Status Register (MSR)
Bit 0 Delta CTS
Bit 1 Delta DSR
Bit 2 Delta RI
Bit 3 Delta CD
Bit 4 CTS
Bit 5 DSR
Bit 6 RI
Bit 7 CD
BASE+7 SPR Temporary data register and indexed control
Register offset value bits