Advantech IDK-2112 Series, User Manual, Page: 20 / 41

IDK-2112 User Manual 14
Note: Output signals from any system shall be low or Hi-Z state when VDD is off.
3.4 Interface Timing
3.4.1 Timing Characteristics
Note1 Frame rate is 60 Hz.
Note2 DE mode.
+BLUE5(B5) Blue Data 5 (MSB)
Blue-pixel Data
Each blue pixel’s brightness data consists of
these 6 bits pixel data.
+BLUE4(B4) Blue Data 4
+BLUE3(B3) Blue Data 3
+BLUE2(B2) Blue Data 2
+BLUE1(B1) Blue Data 1
+BLUE0(B0) Blue Data 0 (LSB)
Blue-pixel Data
CLK Data Clock The typical frequency is 40MHz. The signal is
used to strobe the pixel data and DE signals.
All pixel data shall be valid at the falling edge
when the DE signal is high.
DE Display Timing This signal is strobed at the falling edge of CLK.
When the signal is high, the pixel data shall be
valid to be displayed.
Table 3.2: Timing Characteristics
Signal Symbol Min. Typ. Max. Unit
Clock frequency 1/ T
Clock
34 40 48.3 MHz
Vertical
Section
Period T
V
608 628 1024
T
Line
Active T
VD
- 600 -
Blanking T
VB
8 28 423
Horizontal
Section
Period T
H
960 1056 1060
T
Clock
Active T
HD
- 800 -
Blanking T
HB
220 256 440