Advantech IDK-121R-42XGA1, User Manual, Page: 20 / 41

IDK-1112R User Manual 14
Note: Output signals from any system shall be low or Hi-Z state when VDD is off.
3.3 TFT-LCD Interface Timing
3.3.1 Timing Characteristics
Note Frame rate is 60 Hz.
Note DE mode.
+GREEN5(G5) Green Data 5(MSB) Green-pixel Data
Each green pixel’s brightness data consists of
these 6 bits pixel data.
+GREEN4(G4) Green Data 4
+GREEN3(G3) Green Data 3
+GREEN2(G2) Green Data 2
+GREEN1(G1) Green Data 1
+GREEN0(G0) Green Data 0(LSB)
Green-pixel Data
+BLUE5(B5) Blue Data 5(MSB) Blue-pixel Data
Each blue pixel’s brightness data consists of
these 6 bits pixel data.
+BLUE4(B4) Blue Data 4
+BLUE3(B3) Blue Data 3
+BLUE2(B2) Blue Data 2
+BLUE1(B1) Blue Data 1
+BLUE0(B0) Blue Data 0(LSB)
Blue-pixel Data
CLK Data Clock The typical frequency is 65MHz. The signal is
used to strobe the pixel data and DE signals.
All pixel data shall be valid at the falling edge
when the DE signal is high.
DE Display Timing This signal is strobed at the falling edge of CLK.
When the signal is high, the pixel data shall be
valid to be displayed.
Table 3.2: Timing Characteristics
Parameter Symbol Min. Typ. Max. Unit
Clock frequency 1/ T
Clock
50 65 80 MHz
Vertical
Section
Period T
V
776 806 1023
T
Line
Active T
VD
- 768 -
Blanking T
VB
8 38 255
Horizontal
Section
Period T
H
1054 1344 2047
T
Clock
Active T
HD
- 1024 -
Blanking T
HB
40 320 1023