Advantech IDK-1105 Series, User Manual

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IDK-1105 User Manual 12
3.1 Signal Description
LVDS is a differential signal technology for LCD interface and high speed data trans-
fer device. The connector pin definition is as below.
Note: “Low” stands for 0V. “High” stands for 3.3V. “NC” stands for “Not Connected.”
3.1.1 Signal Description
J2 LVDS connector: CSTAR CP100-S20G-H16
J3 LED connector: ENTERY 3808K-F05N-03L (Mating connector: ENTERY H2808K-
P04N-02B)
Table 3.1: Symbol Description
Pin No. Symbol Description Note
1 VCC Power Voltage for Logic: 3.3V
2 VCC Power Voltage for Logic: 3.3V
3 GND Ground
4 GND Ground
5 IN0- - LVDS differential data input 1
6 IN0+ + LVDS differential data input 1
7 GND Ground
8 IN1- - LVDS differential data input 2
9 IN1+ + LVDS differential data input 2
10 GND Ground
11 IN2- - LVDS differential data input
12 IN2+ + LVDS differential data input
13 GND Ground
14 CLK- -Sampling Clock
15 CLK+ +Sampling Clock
16 GND Ground
17 NC No Connect
18 NC No Connect
19 GND Ground
20 GND Ground
Pin No. Symbol Description Note
1 V
LED
Power Voltage for Backlight: 5V
2 GND Power Ground
3 LED_ON/OFF Backlight ON/OFF, “H” LED ON, “L” LED OFF.
4 PWM PWM input for LED brightness adjustment
ITEM SYMBOL MIN TYP MAX UNIT
ADJ (Dimming) signal frequency fPWM 0.1 -- 200 KHz
ADJ signal logic level High V
ADJL
3 -- 5 V
ADJ signal logic level Low V
ADJL
GND -- 0.3 V