LEC-iMX8M User’s Guide
SGET SMARC Rev 2.1
Page 21
copyright © 2021 ADLINK Technology Inc.
4.3
Signal Description by function
4.3.1
The First Display Interface
The first display interface is a group of 30-pins that is split into a channel 0 and channel 1. The SMARC specification allows to support either dual channel
LVDS ports, 2 separate single channel LVDS ports, 2 MIPI DSI ports of 4 lanes each or 2 eDP ports 4 lanes each. A mix of different display type such as DSI
and
eDP
is
also
permitted.
Below
tables
show
which
display
ports
are
supported
on
this
particular
module
Pin #
LVDS Name
MIPI DSI Name
eDP Name
Pin #
LVDS Name
MIPI DSI Name
eDP Name
S125
S126
S128
S129
S131
S132
S137
S138
LVDS0_0-
LVDS0_1 -
LVDS0_2-
LVDS0_3-
DSI0_D0-
DSI0_D1-
DSI0_D2-
DSI0_D3-
e
eDP0_TX0-
e
eDP0_TX1-
e
eDP0_TX2-
e
eDP0_TX3-
S111
S112
S114
S115
S117
S118
S120
S121
LVDS1_0-
LVDS1_1 -
LVDS1_2-
LVDS1_3-
DSI1_D0-
DSI1_D1-
DSI1_D2-
DSI1_D3-
e
eDP1_TX0-
e
eDP1_TX1-
e
eDP1_TX2-
e
eDP1_TX3-
S134
S135
L
LVDS0_CK-
D
DSI0_CLK-
e
eDP0_AUX-
S108
S109
L
LVDS1_CK-
D
DSI1_CLK-
e
eDP1_AUX-
S133
LCD0_VDD_EN
LCD0_VDD_EN
LCD0_VDD_EN
S116
LCD1_VDD_EN
LCD1_VDD_EN
LCD1_VDD_EN
S127
LCD0_BKLT_EN
LCD0_BKLT_EN
LCD0_BKLT_EN
S107
LCD1_BKLT_EN
LCD1_BKLT_EN
LCD1_BKLT_EN
S141
LCD0_BKLT_PWM
LCD0_BKLT_PWM
LCD0_BKLT_PWM
S122
LCD1_BKLT_PWM
LCD1_BKLT_PWM
LCD1_BKLT_PWM
S144
DSI0_TE
eDP0_HPD
S113
DSI1_TE
eDP1_HPD
S139
I2C_LCD_CK
I2C_LCD_CK
I2C_LCD_CK
S140
I2C_LCD_DAT
I2C_LCD_DAT
I2C_LCD_DAT
Note
: LVDS0/LVDS1 are standard supported through a DSI to LVDS bridge on the module
Note
: DSI0 can be freed up by build option, disabling the LVDS0/LVDS1 ports
