ADLINK Technology SMARC MODULE LEC-EL Product Specification Download Page 14

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ADLINK Technology Inc.

LEC-EL Product specification

Page 14

Block Diagram

BMC/EC

IT5121

4K HDMI /DP

4K DP++ /HDMI

LVDS/DSI/eDP

USB 0,1,4,5

USB 2,3

SATA Gen3

LAN0

LAN1

PCIe A, B, C, D

CAN0

CAN1

14x GPIO

SMB

SDIO

SER 2/3

eSPI

SER 0/1

BOOT Select

SPI

4x I2C

SDIO

HDA/I2S

Power Management

(Elkhart Lake)

Intel Atom® 6

Gen.

USB 2.0 HOST

USB 3.0 HOST

SATA0

DDI2

DDI1

DDI0

GPIO INT

SMB

eSPI

4x PCIex1Gen3

SGMII0

LPDDR4

x32

eMCC

16/32/64GB

CAN

FSPI

I2C

SDIO

HDA/I2S

NXP PTN3460

DSI option

LPDDR4

x32

LPDDR4

x32

LPDDR4

x32

TPM 2.0

Crypto

ATECC608

SPI

I2C

GPY211

SGMII1

SX1509

INT

SDIO

HSUART

SPI BIOS

SPI

Figure 1

–

Module function diagram

Summary of Contents for SMARC MODULE LEC-EL

Page 1: ...LEC EL L 11 08 2021...

Page 2: ...ct descriptions at any time without notice Environmental Responsibility ADLINK is committed to fulfil its social responsibility to global environmental preservation through compliance with the Europea...

Page 3: ...humidity Keep equipment properly ventilated do not block or cover ventilation openings Make sure to use recommended voltage and power source settings Always install and operate equipment near an easi...

Page 4: ...n Page 4 copyright 2021 ADLINK Technology Inc Revision History Revision Description Date dd mm yyyy Author 0 6 Preliminary engineering version 15 03 2021 hp 0 9 Preliminary engineering version updated...

Page 5: ...ader 12 2 9 BIOS 12 2 10 Power 12 2 11 Mechanical and Environmental 13 3 Block Diagram 14 4 Pinout and Signal Descriptions 1 4 1 Pin Summary 1 4 2 Signal Terminology Descriptions 1 4 3 Signal Descript...

Page 6: ...K Technology Inc 4 4 3 CAN bus 13 4 4 4 Miscellaneous 13 4 4 5 Power and System Management 14 4 4 6 Boot Select 16 4 4 7 Power 17 4 5 SMARC pin to controller mapping 18 5 Software Support 29 5 1 1 Yoc...

Page 7: ...LEC EL Product specification SGET SMARC Rev 2 1 Page 7 copyright 2021 ADLINK Technology Inc List of Figures Figure 1 Module function diagram 14 Figure 2 Module top botom side pin numbering 1...

Page 8: ...cally under 6W Two Module sizes are defined 82 mm x 50 mm and 82 mm x 80 mm The Module PCBs have 314 edge fingers that mate with a low profile 314 pin 0 5 mm pitch right angle connector the connector...

Page 9: ...6 MT s memory down type with IBECC 2 2 Video LEC EL standard display support consists of 4K capable HDMI 2 0a 4K DP and single dual channel 24 bit LVDS The LVDS output is derived from an eDP to LVDS b...

Page 10: ...data transfer rates both full duplex and half duplex Secondary LAN GbE1 GPY SOC embedded RGMII Ethernet Controller with optional IEEE 1588 PTP Precision Time Protocol Supports 2 5Gb data transfer rate...

Page 11: ...2C Four I2C interfaces Support for 7 bit and 10 bit address mode Software programmable clock frequency of 100 kbit s in Standard mode 400 kbit s in the Fast mode or 1 Mbit s in Fast mode Plus GPIO 14x...

Page 12: ...er sequencing Basically VDD_IN is the first power domain to be turned on by the carrier circuit during power up Other circuit components on the carrier which are galvanically coupled to the module sha...

Page 13: ...s v2 1 Dimension SMARC small size module 82mm x 50mm Operating Temperature Standard 0 C to 60 C Rugged 40 C to 85 C optional Humidity 5 90 RH operating non condensing 5 95 RH storage and operating wit...

Page 14: ...SDIO SER 2 3 eSPI SER 0 1 BOOT Select SPI 4x I2C SDIO HDA I2S Power Management Elkhart Lake Intel Atom 6th Gen USB 2 0 HOST USB 3 0 HOST SATA0 DDI2 DDI1 DDI0 GPIO INT SMB eSPI 4x PCIex1Gen3 SGMII0 LP...

Page 15: ...y Inc 4 Pinout and Signal Descriptions 4 1 Pin Summary The below tables are a comprehensible list of all signal pins on the MXM 3 connector in the standard specification SMARC 2 1 TOP Side P1 P74 P75...

Page 16: ......

Page 17: ...gnal for MIPI CSI 2 cameras and DSI displays LVDS M PHY Low Voltage Differential Signal for MIPI CSI 3 cameras LVDS LCD Low Voltage Differential Signal for LCD displays LVDS PCIE Low Voltage Different...

Page 18: ...0_D2 DSI0_D3 DSI0_D3 eDP0_TX0 eDP0_TX0 eDP0_TX1 eDP0_TX1 eDP0_TX2 eDP0_TX2 eDP0_TX3 eDP0_TX3 S111 S112 S114 S115 S117 S118 S120 S121 LVDS1_0 LVDS1_0 LVDS1_1 LVDS1_1 LVDS1_2 LVDS1_2 LVDS1_3 LVDS1_3 DSI...

Page 19: ...the signal path usually on the display assembly LCD0_VDD_EN S133 Primary LVDS Channel Power Enable O CMOS 1 8V Runtime Active high LCD0_BKLT_EN S127 Primary LVDS Channel Backlight Enable O CMOS 1 8V R...

Page 20: ...detection and control I O OD CMOS 1 8V Runtime PU 2k2 Possible conflict if two LVDS panels are used I2C_LCD_CK S139 DDC clock line used for flat panel detection and control O OD CMOS 1 8V Runtime PU 2...

Page 21: ...ace Pin HDMI signal names DP signal names P92 P93 P95 P96 P98 P99 HDMI_D2 HDMI_D2 HDMI_D1 HDMI_D1 HDMI_D0 HDMI_D0 DP1_LANE0 DP1_LANE0 DP1_LANE1 DP1_LANE1 DP1_LANE2 DP1_LANE2 P101 P102 HDMI_CK HDMI_CK...

Page 22: ...ups may be part of an integrated HDMI ESD protection and control line level shift device such as the Texas Instruments TPD12S016 If discrete Carrier pull ups are used the value depends on the individ...

Page 23: ...o support the regarding I O voltage This specification ignores the discrepancy between the 1 5V and 1 8V signalling as the chance of damage in mismatched systems is negligible The SMARC HD Audio pins...

Page 24: ...OS 3 3Vsb 3 3V Standby USB1 USB1 P65 P66 USB differential data pairs for port 1 I O USB USB Standby USB1_EN_OC P67 USB over current sense for port 1 I O OD CMOS 3 3Vsb 3 3V Standby PU 10k Pulled low b...

Page 25: ...er current situation USB3_VBUS_DET S37 USB port 3 host power detection when this port is used as a device I USB VBUS 5V USB VBUS 5V Standby USB3_OTG_ID S104 Input pin to announce OTG device insertion...

Page 26: ...OS 3 3V Runtime Can be used for power saving mode on PCIe Pulled up or terminated on Module PCIE_B_TX PCIE_B_TX S90 S91 Differential PCIe link B transmit data pair O LVDS PCIE Runtime Series AC couple...

Page 27: ...ST S77 PCIe Port C reset output O CMOS 3 3V Runtime PCIE_D_TX PCIE_D_TX S29 S30 Differential PCIe link D transmit data pair O LVDS PCIE Runtime Series AC coupled on module PCIE_D_RX PCIE_D_RX S32 S33...

Page 28: ...mments SATA0_TX SATA0_TX P48 P49 Serial ATA channel 0 Transmit Output differential pair O SATA Runtime Series AC coupled on Module 10 nF SATA0_RX SATA0_RX P51 P52 Serial ATA channel 0 Receive Input di...

Page 29: ...0 1 2 3 The MDI can operate in 1000 100 and 10Mbit sec modes Some pairs are unused in some modes according to the following 1000 100 10 _ MDI 0 B1_DA TX TX MDI 1 B1_DB RX RX MDI 2 B1_DC MDI 3 B1_DD GB...

Page 30: ...c modes Some pairs are unused in some modes according to the following 1000 100 10 _ MDI 0 B1_DA TX TX MDI 1 B1_DB RX RX MDI 2 B1_DC MDI 3 B1_DD GBE0_LINK100 P21 Link Speed Indication LED for GBE0 100...

Page 31: ...nd Response This signal is used for card initialization and for command transfers During initialization mode this signal is open drain During command transfer this signal is in push pull mode I O CMOS...

Page 32: ...8V Standby SPI0_DIN P45 SPI0 Master input Slave output I CMOS 1 8V Standby also referred to as MISO SPI0_DO P46 SPI0 Master output Slave input O CMOS 1 8V Standby also referred to as MOSI SPI1_CS0 P5...

Page 33: ...driven from eSPI master to eSPI slaves ESPI_ALERT0 ESPI_ALERT1 S43 S44 ESPI ALERT I OD CMOS 1 8V Standby This pin is used by eSPI slave to request service from eSPI master Alert is an open drain outp...

Page 34: ...in a single big list Below is an overview of all I2C busses and where to find them Name Pin Description Where to find I2C_LCD_DAT S140 DDC data line used for flat panel detection and control LVDS DSI...

Page 35: ...1 8V Runtime PU 470K on the Module Default use is GPIO3 alternative use is Camera 1 Reset active low through DTS GPIO4 HDA_RST P112 General purpose I O pin 4 I O CMOS 1 8V Runtime PU 470K on the Modu...

Page 36: ...andshake line for port 0 I CMOS 1 8V Runtime SER1_TX P134 Asynchronous serial data output port 1 O CMOS 1 8V Runtime SER1_RX P135 Asynchronous serial data input port 1 I CMOS 1 8V Runtime SER2_TX P136...

Page 37: ...1 8V Runtime CAN1_RX P146 CAN port1 Receive input I CMOS 1 8V Runtime 4 4 4 Miscellaneous Name Pin Description I O Type I O Level Power Domain PU PD Comments TEST S157 Held low by Carrier to invoke Mo...

Page 38: ...r supplies other than Module and Carrier power supervisory circuits shall not be enabled while this signal is held low by the Carrier I OD CMOS 1 8V Runtime PU 2 2K Driven by OD on Carrier Module must...

Page 39: ...PM_DAT P122 Power management I2C bus DATA I O OD CMOS 1 8V Runtime PU 2k2 On x86 systems these serve as SMB DATA Pulled up on module I2C_PM_CK P121 Power management I2C bus CLK O OD CMOS 1 8V Runtime...

Page 40: ...CMOS 1 8Vsb Standby PU 10K Driven by OD on Carrier Pulled up on module Low on this pin allows non protected segments of Module boot device to be rewritten restored from an external USB Host on Module...

Page 41: ...tage 4 75 min to 5 25V max P 4 75 to 5 25V GND P2 P9 P12 P15 P18 P32 P38 P47 P50 P53 P59 P68 P79 P82 P85 P88 P91 P94 P97 P100 P103 P120 P133 P142 S3 S10 S16 S25 S34 S47 S61 S64 S67 S70 S73 S80 S83 S86...

Page 43: ...I2_D1_N CSI_P2_VDDHA P12 GND P13 CSI1_RX2 In LVDS D PHY MIPI_CSI2_D2_P CSI_P2_VDDHA P14 CSI1_RX2 In LVDS D PHY MIPI_CSI2_D2_N CSI_P2_VDDHA P15 GND P16 CSI1_RX3 In LVDS D PHY MIPI_CSI2_D3_P CSI_P2_VDDH...

Page 44: ...ALT0 NVCC_ECSPI P44 SPI0_CK Out SPI 1 8V EL x6000 ECSPI2_SCLK ALT0 NVCC_ECSPI P45 SPI0_DIN In SPI 1 8V EL x6000 ECSPI2_MISO ALT0 NVCC_ECSPI P46 SPI0_DO Out SPI 1 8V EL x6000 ECSPI2_MOSI ALT0 NVCC_ECS...

Page 45: ...D33 P77 PCIE_B_CKREQ EL x6000 N C P78 PCIE_A_CKREQ EL x6000 N C P79 GND P80 PCIE_C_REFCK Out EL x6000 N C P81 PCIE_C_REFCK Out EL x6000 N C P82 GND P83 PCIE_A_REFCK Out Serial 0 1uF PCIe EL x6000 DIF3...

Page 46: ...x6000 GPIO1_IO05 ALT0 NVCC_GPIO1 P110 GPIO2 CAM0_RST Out PU 470K GPIO 1 8V EL x6000 GPIO1_IO06 ALT0 NVCC_GPIO1 P111 GPIO3 CAM1_RST Out PU 470K GPIO 1 8V EL x6000 GPIO1_IO06 ALT0 NVCC_GPIO1 P112 GPIO4...

Page 47: ...RT3_TXD ALT0 NVCC_UART P141 SER3_RX In UART 1 8V EL x6000 UART3_RXD ALT0 NVCC_UART P142 GND P143 CAN0_TX Out CAN EL x6000 TXCAN VDD_3V3 P144 CAN0_RX In CAN EL x6000 RXCAN VDD_3V3 P145 CAN1_TX EL x6000...

Page 48: ..._D1_P MIPI_CSI1_VDDHA S15 CSI0_RX1 In MIPI CSI EL x6000 MIPI_CSI1_D1_N MIPI_CSI1_VDDHA S16 GND S17 GBE1_MDI0 Bi Dir GBE MDI GPY MDI_PLUS 0 S18 GBE1_MDI0 Bi Dir GBE MDI GPY MDI_MINUS 0 S19 GBE1_LINK100...

Page 49: ...0 I2C3_SCL ALT0 NVCC_I2C S49 I2C_GP_DAT Bi Dir PU 2 2K I2C3 EL x6000 I2C3_SDA ALT0 NVCC_I2C S50 HDA_SYNC I2S2_LRCK SAI 1 8V EL x6000 SAI3_TXFS ALT0 NVCC_SAI3 S51 HDA_SDO I2S2_SDOUT SAI 1 8V EL x6000 S...

Page 50: ...IE_C_TX SERDES_2_TX EL x6000 N C S82 PCIE_C_TX SERDES_2_TX EL x6000 N C S83 GND S84 PCIE_B_REFCK Out Serial 0 1uF PCIe EL x6000 DIF1 VDDDIG1p8 S85 PCIE_B_REFCK Out Serial 0 1uF PCIe EL x6000 DIF1 VDDD...

Page 51: ...DSI1_D1 Out Serial 0R LVDS PTN3460 B_Y1P S115 LVDS1_1 eDP1_TX1 DSI1_D1 Out Serial 0R LVDS PTN3460 B_Y1N S116 LCD1_VDD_EN N C N C S117 LVDS1_2 eDP1_TX2 DSI1_D2 Out Serial 0R LVDS PTN3460 B_Y2P S118 LV...

Page 52: ...t PU 2 2K I2C4 EL x6000 I2C4_SCL ALT0 NVCC_I2C S140 I2C_LCD_DAT Bi Dir PU 2 2K I2C4 EL x6000 I2C4_SCL ALT0 NVCC_I2C S141 LCD0_BKLT_PWM Out GPIO 1 8V EL x6000 GPIO1_IO01 ALT1 NVCC_GPIO1 S142 GPIO12 In...

Page 53: ...e 29 copyright 2021 ADLINK Technology Inc 5 Software Support 5 1 1 Yocto Yocto is available from Adlink Github https github com ADLINK meta adlink x86 64bit 5 1 2 Ubuntu Ubuntu is supported from kerne...

Page 55: ...e 31 copyright 2021 ADLINK Technology Inc 7 Thermal Solutions For optimum performance LEC EL has to be cooled by a passive Heatsink Heat spreader optionally available for ordering HTS sEL Heatspreader...

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