ADLINK Technology SMARC LEC-PX30, User Manual

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LEC- PX30 User’s Guide SGET SMARC Rev 2.1
Page 25 copyright © 2020 ADLINK Technology Inc.
4.3.4 Audio
4.3.4.1 I2S0 / I2S2
Name Pin # Description I/O
Type I/O
Level Power
Domain PU /
PD Comments
I2S0_LRCK S39 I2S0 Left & Right synchronization
clock I/O
CMOS 1.8V Runtime Module Output if CPU acts in Master Mode
Module Input if CPU acts in Slave Mode
I2S0_SDOUT S40 I2S0 Digital audio Output O
CMOS 1.8V Runtime
I2S0_SDIN S41 I2S0 Digital audio Input I
CMOS 1.8V Runtime
I2S0_CK S42 I2S0 Digital audio clock I/O
CMOS 1.8V Runtime Module Output if CPU acts in Master Mode
Module Input if CPU acts in Slave Mode
I2S2_LRCK /
HDA_SYNC S50 I2S2 Left & Right synchronization
clock I/O
CMOS 1.8V Runtime Module Output if CPU acts in Master Mode
Module Input if CPU acts in Slave Mode
I2S2_SDOUT/
HDA_SDO S51 I2S2 Digital audio Output O
CMOS 1.8V Runtime
I2S2_SDIN/
HDA_SDI S52 I2S2 Digital audio Input I
CMOS 1.8V Runtime
I2S2_CK/
HDA_CK S53 I2S2 Digital audio clock I/O
CMOS 1.8V Runtime Module Output if CPU acts in Master Mode
Module Input if CPU acts in Slave Mode
AUDIO_MCK S38 Master clock output to I2S
codec(s) O
CMOS 1.8V Runtime
Note : I2S1 signalling has been removed during update to SMARC 2.0 specification