18
Register
Format
CH1 Int_EN (bit 10): Write/Read
DI channel 1 interrupt enable control
1 : enable
0 : disable
All possible combinations of interrupt source are shown as follows.
3.8 Interrupt Status Register
When interrupt occurs, provides information to determine interrupt
status and interrupt setup condition.
Address: BASE + 0x08
Attribute: Read
Interrupt
Bit 10
Bit 9 Bit 8 IRQ Source
IRQ Trigger
Condition
Disable
0
0
0
Interrupt disable
--
Mode 1
0
0
1
COS interrupt
Change of state in
enabled channel
Mode 2
0
1
0
Ch.0 interrupt enable
Rising edge of DI
channel 0
Mode 2
1
0
0
Ch.1 interrupt enable
Rising edge of DI
channel 1
Mode 2
1
1
0
Ch.0 & 1 interrupt
enable
Rising edge of DI
channel 0 or 1
Forbidden
0
1
1
Not allowed (disable) ---
1 0
1 1
7
6
5
4
3
2
1
0
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CH1 Int. Status CH0 Int. Status COS Int. Status