ADLINK Technology NuPRO-900A, User Manual, Page: 15 / 49

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Introduction
1.3.1 Intel® Low Power Xeon™ Processor
The Intel® Xeon™ processor for dual-processing servers offers users several
new system performance boosts, with the Intel Netburst micro-architecture on
Intel's 0.13-micron manufacturing process, Hyper-Threading technology, a
larger (512 KB) level two-cache size and the E7500 server chipset. The Intel®
Xeon™ processor family is the first to feature the new, innovative technologies
of Hyper-Threading Technology and Intel® NetBurst™ micro-architecture,
providing headroom for current and future server and workstation platforms.
The Intel® NetBurst™ micro-architecture and Hyper-Threading Technology is
designed specifically for multi-tasking environments and provides outstanding
performance for multi-threaded applications.
1.3.2 The Intel® E7500 Chipset Memory Controller Hub (MCH)
The central hub for all data passing through core system elements such as the
dual Intel® Xeon™ processors with 512 KB L2 cache via the system bus
interface, the memory via memory interface, and both the 64-bit PCI/PCI-X and
I/O controller hubs via Intel® Hub Interfaces. The Intel E7501 chipset delivers
compelling performance at 3.2GB/s of bandwidth across the 400/533MHz
system bus and up to 3.2GB/s of bandwidth across two high-performance
Double Data Rate SDRAM memory channels. To balance the performance
offered by the processor and memory interfaces, the MCH allows several
high-bandwidth I/O configuration options for a total of 3.2GB/s of I/O
bandwidth. Together, these features deliver balanced, high-throughput system
performance for dual processor server platforms.
1.3.3 The Intel® 82801CA I/O Controller Hub 3-S (ICH3-S)
Connect to the MCH through a point-to-point Hub Interface 1.5 connection.
The ICH3-S provides legacy I/O interfaces through integrated features
including a two-channel Ultra ATA/100 bus master IDE controller and a USB
controller for two USB ports. The ICH3-S also offers an integrated System
Manageability Bus 2.0 (SMBus 2.0) controller, an integrated LAN controller, as
well as a PCI 2.2-compliant interface CMG 2.1 Hot Swap Support
1.3.4 Watchdog Timer
The watchdog timer optionally monitors system operation and can be
programmed for different timeout periods (from 1 seconds to 255 seconds or 1
minute to 255 minutes). The watchdog is capable generating a Reset. Failure
to strobe the watchdog timer within the programmed time period may result in a
reset request. A register bit can be enabled to indicate if the watchdog timer
caused the reset event. This watchdog timer register is cleared on power-up,
enabling system software to take appropriate action if the watchdog generated
the reboot.