ADLINK Technology NuDAQ cPCI-7249R, User Manual, Page: 44 / 74

30 Operation Theory
72XX Series

User’s Manual
4.2.2 General Purpose Timer/Counter
The counter 0 is a general purpose timer/counter for users appli-
cations. It can be used as an event counter, for measuring fre-
quency, or other functions. The following Modes are provided by
the 82C54 chip.
 Mode 0 : Interrupt on Terminal Count
 Mode 1 : Programmable One-Shot
 Mode 2 : Rate Generator
 Mode 3 : Square Wave Rate Generator
 Mode 4 : Software Triggered Strobe
 Mode 5 : Hardware Triggered Strobe
The 8254 timer/counter IC occupies four I/O addresses. Users can
refer to Tundra's or Intel®'s data sheet for a full description of the
8254 features. You can download the 8254 data sheet from the
following web site:
http://support.intel.com/support/controllers/peripheral/231164.htm
or
http://www.tundra.com (for Tundra’s 82C54 datasheet)
4.2.3 Cascaded 32 Bits Timer
The input clock frequency of the cascaded timers is 2MHz. The
output of the timer is sent to the interrupt circuit (refer to section
4.3). Therefore, the maximum and minimum watchdog timer inter-
rupt frequency is (2MHz)/(2*2)=500KHz and (2MHz)/
(65535*65535)= 0.000466Hz respectively.
4.2.4 Event Counter and Edge Control
The counter #0 of the 8254 chip can be used as an event counter.
The input of counter #0 is PC4 of CN1 (P1C4). The counter clock
trigger direction (H to L or L to H) is programmable. The gate con-
trol is always enabled. The output is sent to interrupt system which
is named as event IRQ. If counter #0 is set as 8254 mode 0, the
event counter IRQ will generate when the counter value is count-
ing down to zero.