ADLINK Technology MCM-100, User Manual

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Operation 37
MCM-100/102
4.1.2 AI Data Format
When an A/D converter is used, properties of the signal to be
measured must be ascertained to determine the channel to be
used and connections to the card. After A/D conversion, the A/D
data is buffered in a Data FIFO, for transfer to memory for further
processing. Transfer characteristics of various input ranges of the
MCM-100/102 are as follows, with data format 2’s complement.
Table 4-2: MCM-100/102 Input Ranges
4.1.3 Sampling Rate
To drive the sigma-delta ADC, an onboard timebase clock is
applied, with frequency exceeding the sampling rate, produced
from a DDS (Direct Digital Synthesis) chip. The output frequency
of the DDS chip is programmable, with excellent resolution.
DDS Timing/Sampling Rate
Description
Bipolar Analog
Input Range
Digital Code
Full-scale Range ±10V
Least significant bit 1.19uV
FSR-1LSB
9.99999881V 7FFFFFh
Mi1LSB 1.19uV 000001h
Midscale 0V 000000h
Midscale –1LSB -1.19uV FFFFFFh
-FSR -10V 800000h
Mode High Resolution High Speed
Sampling Rate 1 kHz ~ 52.734 kHz 52.734 kHz ~ 128
kHz
fCLK/fDATA 512 256
DDS CLK 512kHz to
26.999808MHz 13.499904 MHz to
2.768 MHz
Sampling Rate
Resolution 0.0003 Hz 0.0003 Hz