ADLINK Technology Express-BD74 User Manual Download Page 82

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BIOS Setup

7.4.5.3. Chipset > PCH Configuration > PCH SATA Configuration

Feature

Options

Description

PCH SATA Configuration

Info only

Configure SATA as

IDE

AHCI

Identify the SATA port is connected to Solid State
Drive or Hard Disk Drive

SATA test mode

Enabled

Disabled

Enable/Disable SATA test mode

SATA Mode options

Submenu

SATA AHCI LPM

Disabled
Enabled

Enable/Disable Link Power Management

SATA Controller Speed

Default
Gen1

Gen2

Gen3

Indicates the maximum speed the SATA controller can
support.

SATA Port 0-1

Info only

Software Preserve

Info only

Port 0-1

Disabled

Enabled

Enable or Disable SATA Port

Hot Plug

Disabled

Enabled

Designates this port as Hot Pluggable.

Configure as eSATA

Disabled

Enabled

Configures port as External SATA (eSATA)

Configured as eSATA

Info only

Spin Up Device

Disabled

Enabled

If enabled for any of ports Staggered Spin Up will be
performed and only the drives which have this option
enabled will spin up at boot. Otherwise all drives spin
up at boot.

SATA Device Type

Hard Disk Drive

Solid State Drive

Identify the SATA port is connected to Solid State
Drive or Hard
Disk Drive

Summary of Contents for Express-BD74

Page 1: ...GE COMPUTING Express BD74 User s Manual COM Express Basic Size Type 7 Module with up to 16 core Intel Xeon D Processor and Four SODIMM sockets Manual Rev 1 1 Revision Date May 25 2020 Part Number 50 1...

Page 2: ...LINK is committed to fulfill its social responsibility to global environmental preservation through compliance with the European Union s Restriction of Hazardous Substances RoHS directive and Waste El...

Page 3: ...er 5 2 10 Debug 5 2 11 Power Specifications 6 2 12 Operating Temperatures 6 2 13 Environmental 6 2 14 Specification Compliance 6 2 15 Operating Systems 6 2 16 Functional Diagram 7 2 17 Mechanical Draw...

Page 4: ...rrupt Mapping 42 6 6 PCI Configuration Space Map 43 6 7 PCI Interrupt Routing Map 44 6 8 SMBus Address Table 44 7 BIOS Setup 45 7 1 Menu Structure 45 7 2 Main 46 7 3 Advanced 48 7 4 Chipset 63 7 5 Sec...

Page 5: ...ram 7 Figure 2 Express BD74 Mechanical Drawing 8 Figure 3 Express BD74 Connector Switch and LED Locations 25 Figure 4 Express BD74 and the DB40 Debug Module 26 Figure 5 Express BD74 Switch Locations 3...

Page 6: ...nnector Pin Definition 27 Table 3 Express BD74 LED Descriptions 28 Table 5 Fan Connector Pin Definition 29 Table 6 BIOS Select and Mode Configuration Switch Settings 31 Table 7 SEMA Onboard Voltage Mo...

Page 7: ...DIMMs to provide a maximum of 128GB DDR4 ECC or non ECC memory capacity and dual channel memory design at 1866 2133 2400 MHz dependent on SoC SKU for excellent overall performance An integrated Intel...

Page 8: ...2 Introduction This page intentionally left blank...

Page 9: ...for D1577 18MB for D1559 12MB for D1548 D1539 Memory Dual channel ECC or non ECC 1866 2133 2400 MHz DDR4 memory up to 128GB in four SODIMM sockets two on top two on bottom Note Supported memory freque...

Page 10: ...icating ACT LINK Speed 10G_SFP_SDA and 10G_SFP_SCL dedicated for Optical PHY use connect to external SFP module 10G_SDP Software Definable Pin for general purpose 2 4 Gigabit Ethernet Intel Controller...

Page 11: ...ed by Super I O W83627DHG on carrier board 4 0x3F8 Yes COM 4 Supported by Super I O W83627DHG on carrier board 3 0x2F8 Yes 2 8 Trusted Platform Module TPM z Chipset Infineon z Type TPM 2 0 2 9 SEMA Bo...

Page 12: ...0 C to 80 C Extreme Rugged Operating Temperature optional 40 C to 85 C Standard Voltage Input dependent on SoC SKU build option support Storage 40 C to 85 C 2 13 Environmental Humidity Operating 5 90...

Page 13: ...2 3 4x USB 3 0 upgrade port 0 1 2 3 UART0 1 SPI 1 BIOS 1 PCIe lane Gen2 port 6 SPI_CS 1x 10G KR 1x 10G KR 6 PCIe lanes Gen2 port 0 5 New SEMA BMC GPIO PCA9535 SODIMM 2 4 Up to 2400 MHz 4 32 GB ECC non...

Page 14: ...28 33 0 4 80 16 5 74 2 121 87 0 125 8 35 87 25 31 655 71 152 Bottom Side RAM Module Keepout Bottom View All dimensions are shown in millimeters Tolerances should be 0 25mm unless otherwise noted The t...

Page 15: ...GND fixed C11 GND fixed D11 GND fixed A12 GBE0_MDI0 B12 PWRBTN C12 USB_SSRX3 D12 USB_SSTX3 A13 GBE0_MDI0 B13 SMB_CK C13 USB_SSRX3 D13 USB_SSTX3 A14 GBE0_CTREF B14 SMB_DAT C14 GND D14 GND A15 SUS_S3 B1...

Page 16: ...TX16 A54 GPI0 B54 GPO1 C54 TYPE0 D54 RSVD A55 PCIE_TX4 B55 PCIE_RX4 C55 PCIE_RX17 D55 PCIE_TX17 A56 PCIE_TX4 B56 PCIE_RX4 C56 PCIE_RX17 D56 PCIE_TX17 A57 GND B57 GPO2 C57 TYPE1 D57 TYPE2 A58 PCIE_TX3...

Page 17: ...GND A94 SPI_CLK B94 NCSI_CRS_DV C94 PCIE_RX29 D94 PCIE_TX29 A95 SPI_MOSI B95 NCSI_TXD1 C95 PCIE_RX29 D95 PCIE_TX29 A96 TPM_PP B96 NCSI_TXD0 C96 GND D96 GND A97 TYPE10 B97 SPI_CS C97 RSVD D97 RSVD A98...

Page 18: ...O 5V Output 5V signal level I O 3 3V Bi directional signal 3 3V tolerant I O 5V Bi directional signal 5V tolerant I O 3 3Vsb Input 3 3V tolerant active in standby state P Power Input Output REF Refere...

Page 19: ...Controller 0 Media Dependent Interface Differential Pairs 0 1 2 3 The MDI can operate in 1000 100 and 10Mbit sec modes Some pairs are unused in some modes according to the following 1000BASE T 100BAS...

Page 20: ...CIE_TX2 PCIE_TX2 A61 A62 PCI Express channel 2 Transmit Output differential pair O PCIE AC coupled on Module PCIE_RX2 PCIE_RX2 B61 B62 PCI Express channel 2 Receive Input differential pair I PCIE AC c...

Page 21: ...CIE_TX14 A25 A26 PCI Express channel 14 Transmit Output differential pair O PCIE AC coupled on Module PCIE_RX14 PCIE_RX14 B25 B26 PCI Express channel 14 Receive Input differential pair I PCIE AC coupl...

Page 22: ...lient may detect the presence of a USB host on USB0 A high value indicates that a host is present I 3 3VSB Not Supported Limitation of this platform 3 3 7 USB Root Segmentation All USB from XHCI contr...

Page 23: ...internal pull down This signal is used to indicate Physical Presence to the TPM I 3 3V PD 100k 3 3V PD only when TPM on module 3 3 10 SMBus Signal Pin Description I O PU PD Comment SMB_CK B13 System...

Page 24: ...TTL level input I CMOS PU 10k 5V Power rail tolerance 5V 12V SER1_TX A101 General purpose serial port transmitter TTL level output O CMOS PU 1k 5V Power rail tolerance 5V 12V SER1_RX A102 General purp...

Page 25: ...ernal power management event I 3 3VSB PU 10k 3 3VSB LID A103 LID button Low active signal used by the ACPI operating system for a LID switch I OD 3 3VSB PU 47k 3 3VSB SLEEP B103 Sleep button Low activ...

Page 26: ...d USB data path on USB2 I PCIE AC coupled off module USB_SSTX2 USB_SSTX2 D9 D10 Additional Transmit signal differential pairs for the SuperSpeed USB data path on USB2 O PCIE AC coupled on module USB_S...

Page 27: ...U 2 2k 3 3VSB MDIO Mode Management Data I O Interface mode clock signal for serial data transfers between the MAC and an external PHY O 3 3VSB 10G_PHY_MDC_SCL0 C46 I 2 C Mode I 2 C Data signal of the...

Page 28: ...signals and additional Strapping signal for I2 C or MDIO mode of Optical PHY I O OD 3 3VSB PU 2 2k 3 3VSB LED signals for 10GbE port 2 3 are also transferred through this pin 10G_LED_SCL C37 I2 C Clo...

Page 29: ...C79 PCI Express channel 24 Receive Input differential pair I PCIE AC coupled off Module PCIE_TX25 PCIE_TX25 D81 D82 PCI Express channel 25 Transmit Output differential pair O PCIE AC coupled on Module...

Page 30: ...NC NC GND Pinout Type 3 no IDE NC GND NC Pinout Type 4 no PCI NC GND GND Pinout Type 5 no IDE no PCI GND NC NC Pinout Type 6 no IDE no PCI GND NC GND Pinout Type 7 server level with 10GbE The Carrier...

Page 31: ...ule but are not included in the PICMG standard specification Note For SODIMM keep out zone information please refer to 2 17 Mechanical Drawing on page 8 4 1 Connector Switch and LED Locations 40 pin M...

Page 32: ...26 Connectors LEDs and Switches Express BD74 and the DB40 Debug Module For illustration purposes only Figure 4 Express BD74 and the DB40 Debug Module...

Page 33: ...ent 34 SPI Program interface SPI_BIOS_CLK 14 OCD0A 33 3V3_LPC 13 BMC Program interface cont d OCD0B 32 GND 12 PWRBTN PU 10k 3 3VSB 31 BIOS_DIS0 PU 10k 3 3VSB 11 SYS_RESET PU 10k 3 3VSB 30 RST 10 CB_RE...

Page 34: ...ption Codes below LED2 Green Power Source 3Vcc S0 LED ON S3 S4 S5 LED OFF ECO mode LED OFF LED3 Red BMC output and same signal as WDT B27 on BtB connector Module power up LED OFF Watchdog counting Kee...

Page 35: ...Connectors LEDs and Switches 29 4 4 Fan Connector Connector Type JVE 24W1125A 04M00 Pin Orientation 1 2 3 4 Pin Assignment Name Signal 1 FAN_PWMOUT 2 FAN_TACHIN 3 Ground 4 5V Table 4 Fan Connector Pi...

Page 36: ...perform the following steps 1 Shut down the system 2 Press the BIOS Setup Defaults RESET Button continuously and boot up the system You can release the button when the BIOS prompt screen appears 3 The...

Page 37: ...n PICMG mode a BIOS chip cannot be placed in the SPI0 slot on the carrier In dual BIOS Failsafe mode both BIOS chips on the module are configured as SPI1 Only one of the two is connected to the SPI bu...

Page 38: ...ation IIO0 Configuration IOU1 IIO PCIe Port 3 to x8x8 PCIex16 to two x8 Adapter Card Model P16TO28 Part No 91 79301 0010 4 8 PCIe x8 to two x4 Adapter Card The Express BD74 can be used with the PCIe x...

Page 39: ...are stored in flash Power cycles counter Boot counter Counts the number of boot attempts Watchdog Timer Set Reset Disable Watchdog Timer Features auto reload at power up System Restart Cause Power lo...

Page 40: ...SEMA Onboard Voltage Monitor 5 1 2 Main Current The BMC of the Express BD74 implements a current monitor The current can be read by calling the SEMA function Get Main Current The function returns fou...

Page 41: ...is removed Therefore a Clear Exception Code command is not needed or supported Exception Code Error Message 0 NOERROR 2 NO_SUSCLK 3 NO_SLP_S5 4 NO_SLP_S4 5 NO_SLP_S3 6 BIOS_FAIL 7 RESET_FAIL 8 RESETIN...

Page 42: ...C Flags The BMC Flags register returns the last detected Exception Code since power up and shows the BIOS in use and the power mode Bit Description 0 4 Exception Code 6 0 AT mode 1 ATX mode 7 0 Standa...

Page 43: ...ble PAE set FEC4 8000h FEC4 FFFFh PCI Express Port 8 PCI Express Root Port 8 I OxAPIC Enable PAE set FEC0 0000h FFC7 FFFFh FF80 0000h FF87 FFFFh LPC or SPI or PCI Bit 8 in BIOS Decode Enable register...

Page 44: ...sm D30 F0 64 KB anywhere in 4 GB range LPC LPC Generic Memory Range Enable using setting bit 0 of the LPC Generic Memory Range register D31 F0 offset 98h 32 Bytes anywhere in 64 bit address range SMBu...

Page 45: ...009 00E DMA Controller 0F DMA Controller 010 018 DMA Controller 019 01E DMA Controller 020 021 Interrupt Controller 024 025 Interrupt Controller 028 029 Interrupt Controller 02C 02D Interrupt Controll...

Page 46: ...0A8 0A9 0AC 0AD Interrupt Controller 0B0 0B1 0B4 0B5 0B8 0B9 0BC 0BD Interrupt Controller 0B2 0B3 Power Management 0C0 0D1 0D2 0DD 0DE 0DF DMA Controller 0F0 FERR Interrupt Controller 170 177 SATA Co...

Page 47: ...es above ACPI Base TCO Anywhere in 64 KB I O Space GPIO 3 Ranges in 64 KB I O Space Parallel 8 Ranges in 64 KB I O Space Serial Port 1 8 Ranges in 64 KB I O Space Serial Port 2 2 Ranges in 64 KB I O S...

Page 48: ...es 13 FERR logic No 14 SATA Primary Yes 15 SATA Secondary Yes 16 Internal devices are routable PIRQA 17 Internal devices are routable PIRQB 18 Internal devices are routable PIRQC 19 Internal devices a...

Page 49: ...1Dh 00h USB EHCI Controller 1 00h 1Ch 00h PCI Express Port 1 00h 1Ch 01h PCI Express Port 2 00h 1Ch 02h PCI Express Port 3 00h 1Ch 03h PCI Express Port 4 00h 1Ch 04h PCI Express Port 5 00h 1Ch 05h PCI...

Page 50: ...Int0 INTA 16 INTB 17 INTC 18 INTD 19 INTA 16 INTB 17 INTC 18 INTD 19 Int1 INTB 17 INTC 18 INTD 19 INTA 16 INTB 17 INTC 18 INTD 19 INTA 16 Int2 INTC 18 INTD 19 INTA 16 INTB 17 INTC 18 INTD 19 INTA 16 I...

Page 51: ...nformation Board Information System Date and Time Access Level Power Management System Management Thermal Management Watchdog Timer CSM Configuration Super IO Configuration Serial Console Redirection...

Page 52: ...sion Info only ADLINK BIOS version Build Date Info only ADLINK BIOS Build Date SPS Firmware Version Info only Display SPS Firmware Version BIOS Boot Source Info only Display BIOS Boot Source 7 2 2 Mai...

Page 53: ...ate Current Runtime Info only The returned value specifies the time in seconds the system is running in S0 state This counter is cleared when the system is removed from the external power supply Power...

Page 54: ...it will make OS show shutdown LID Function Disabled Enabled Enable Disable LID Function Lock Legacy Resource Disabled Enabled Enables or Disables Lock of Legacy Resources I21x Lan Power Ctrl PC2 PC1...

Page 55: ...d Features Info only Display SEMA Supported Features Flags Submenu Flag Flags Info only BMC Flags Info Only BIOS Select Info Only ATX AT Mode Info Only Exception Code Info Only 7 3 4 Advanced Thermal...

Page 56: ...emperature Max Info Only Display Max Board Temperature CPU Fan Speed Info Only Display CPU Fan Speed 7 3 4 2 Advanced Thermal Management Smart Fan Feature Options Description Smart Fan Info Only CPU S...

Page 57: ...y UEFI only This option controls Legacy UEFI ROMs priority Option ROM execution Info only Network Do not launch UEFI Legacy Controls the execution of UEFI and Legacy PXE OpROM Storage Do not launch UE...

Page 58: ...rt 2 COMB Serial Port 2 Configuration Info only Serial Port Disableed Enabled Enable or Disable Serial Port COM Device Settings Info Only Display IO IRQ information of COM Port Change Settings Auto IO...

Page 59: ...rial Port 2 COMB Serial Port 2 Configuration Info only Serial Port Disableed Enabled Enable or Disable Serial Port COM Device Settings Info Only Display IO IRQ information of COM Port Change Settings...

Page 60: ...isabled Console Redirection Enable or Disable Console Redirection Settings Submenu The settings specify how the host computer and the remote computer which the user is using will exchange data Both co...

Page 61: ...do not allow for error detection They can be used as an additional data bit Stop Bits 1 2 Stop bits indicate the end of a serial data packet A start bit indicates the beginning The standard setting i...

Page 62: ...rs Even parity bit is 0 if the num of 1 s in the data bits is even Odd parity bit is 0 if num of 1 s in the data bits is odd Mark parity bit is always 1 Space Parity bit is always 0 Mark and Space Par...

Page 63: ...s may require lower speeds Data Bits 7 8 Data Bits Parity None Even Odd Mark Space A parity bit can be sent with the data bits to detect some transmission errors Even parity bit is 0 if the num of 1 s...

Page 64: ...Uses UTF8 encoding to map Unicode chars onto 1 or more bytes Bits per second 9600 19200 38400 57600 115200 Selects serial port transmission speed The speed must be matched on the other side Long or no...

Page 65: ...lumns supported redirection Putty KeyPad VT100 Intel Linux XTERMR6 SCO ESCN VT400 Select FunctionKey and KeyPad on Putty Redirection After BIOS POST Always Enable BootLoader When Bootloader is selecte...

Page 66: ...Disabled Enabled This is a workaround for Oses without EHCI hand off support The EHCI ownership change should be claimed by EHCI driver USB Mass Storage Driver Support Disableed Enabled Enable Disabl...

Page 67: ...Disable Battery Function I2C write protect control Active Write protect I2C write protect control Above 4G Decoding Disabled Enabled Enabls or Disables 64bit capable Devices to be Decode in Above 4G A...

Page 68: ...Platform hierarchy Disable Enable Enable or Disable Platform Hierarchy Storage Hierarchy Disable Enable Enable or Disable Storage Hierarchy Endorsement Hierarchy Disable Enable Enable or Disable Endor...

Page 69: ...information L3 Cache RAM Info only Display L3 Cache RAM information Processor 0 Version Info only Display Processor 0 Version information Hyper Threading ALL Disable Enable Enable Hyper Threading Soft...

Page 70: ...Window aka Power Limit 1 Time value in seconds The value may vary from 0 to 56 Indicates the time window over which TDP value should be maintained If the value is 0 the fused value will be programed 7...

Page 71: ...le Disable CPU C3 ACPI C2 report to OS Recommended to be disabled CPU C6 report Disable Enable Enable Disable CPU C6 ACPI C2 report to OS Recommended to be enabled Enhanced Halt State C1E Disable Enab...

Page 72: ...o bring up the Intel VT for Directed I O VT d Configuration menu 7 4 4 1 Chipset IIO Configuration IIO0 Configuration Feature Options Description IOU2 IIO PCIe Port 1 x4x4 x8 Auto Select PCIe port Bif...

Page 73: ...B De Emphasis control LNKCON2 6 for this PCIe port PCI E Port Link Status Info only PCI E Port Link Max Info only PCI E Port Link Speed Info only PCI E ASPM Support Auto Disable L1 Only This option en...

Page 74: ...3 5 dB PCIe Gen3 Downstream Tx Present Gen3 DN Rx Preset Hint Auto P0 6 0 dB P1 7 0 dB P2 8 0 dB P3 9 0 dB P4 10 0 dB P5 11 0 dB P6 12 0 dB PCIe Gen3 Downstream Rx Present Hint Gen3 UP Tx Preset Auto...

Page 75: ...B De Emphasis control LNKCON2 6 for this PCIe port PCI E Port Link Status Info only PCI E Port Link Max Info only PCI E Port Link Speed Info only PCI E ASPM Support Auto Disable L1 Only This option en...

Page 76: ...3 5 dB PCIe Gen3 Downstream Tx Present Gen3 DN Rx Preset Hint Auto P0 6 0 dB P1 7 0 dB P2 8 0 dB P3 9 0 dB P4 10 0 dB P5 11 0 dB P6 12 0 dB PCIe Gen3 Downstream Rx Present Hint Gen3 UP Tx Preset Auto...

Page 77: ...B De Emphasis control LNKCON2 6 for this PCIe port PCI E Port Link Status Info only PCI E Port Link Max Info only PCI E Port Link Speed Info only PCI E ASPM Support Auto Disable L1 Only This option en...

Page 78: ...3 5 dB PCIe Gen3 Downstream Tx Present Gen3 DN Rx Preset Hint Auto P0 6 0 dB P1 7 0 dB P2 8 0 dB P3 9 0 dB P4 10 0 dB P5 11 0 dB P6 12 0 dB PCIe Gen3 Downstream Rx Present Hint Gen3 UP Tx Preset Auto...

Page 79: ...Engine Coherency support Coherency Support Isoch Enable Disable Enable Disable Isoch VT_D Engine Coherency support 7 4 5 Chipset PCH Configuration Feature Options Description PCH Configuration Info o...

Page 80: ...Scream Disabled Enabled When Enabled DS packets on DMI with the EP bit set will have their UT bit set LAN PCIE Port used None Subtractive Decode Disabled PCIe USB Glitch W A Disabled Enabled PCIe USB...

Page 81: ...isabled Enabled PCI Express Completion Timer TO Enable Disable SEFE Disabled Enabled Root PCI Express System Error on Fatal Error Enable Disable SENFE Disabled Enabled Root PCI Express System Error on...

Page 82: ...aximum speed the SATA controller can support SATA Port 0 1 Info only Software Preserve Info only Port 0 1 Disabled Enabled Enable or Disable SATA Port Hot Plug Disabled Enabled Designates this port as...

Page 83: ...abled Enabled Control each of the USB ports 0 13 disabling XHCI Idle L1 Enabled Disabled Enabled XHCI Idle L1 Disabled to workaround USB3 hot plug will fail after 1 hot plug removal Please put the sys...

Page 84: ...nu Customizable Secure Boot settings System Mode Info only Secure Boot Info only Vender Keys Info only Attempt Secure Boot Disabled Enabled Secure Boot activated when Platform Key PK is enrolled Syste...

Page 85: ...ped to reduce time cost during boot New Boot Option Policy Default Place First Place Last Controls the placement of newly detected UEFI boot option 7 6 1 Boot FIXED BOOT ORDER Priorities Feature Optio...

Page 86: ...Save Change and Reset Reset the system after saving the changes Discard Changes and Reset Reset system setup without saving any changes Save Options Info only Save Changes Save Changes done so far to...

Page 87: ...by the Intel Platform Innovation Framework for EFI the Framework The Framework refers the following boot phases which may apply to various status code checkpoint descriptions Security SEC initial low...

Page 88: ...overy errors PEI 8 2 Standard Status Codes 8 2 1 SEC Phase Status Code Description 0x00 Not used Progress Codes 0x01 Power on Reset type detection soft hard 0x02 AP initialization before microcode loa...

Page 89: ...th Bridge initialization North Bridge module specific 0x19 Pre memory South Bridge initialization is started 0x1A Pre memory South Bridge initialization South Bridge module specific 0x1B Pre memory So...

Page 90: ...ge module specific 0x3F 0x4E OEM post memory initialization codes 0x4F DXE IPL is started PEI Error Codes 0x50 Memory initialization error Invalid memory type or incompatible memory speed 0x51 Memory...

Page 91: ...ocess started 0xF3 Recovery firmware image is found 0xF4 Recovery firmware image is loaded 0xF5 0xF7 Reserved for future AMI progress codes Recovery Error Codes 0xF8 Recovery PPI is not available 0xF9...

Page 92: ...ecific 0x6E North Bridge DXE initialization North Bridge module specific 0x6F North Bridge DXE initialization North Bridge module specific 0x70 South Bridge DXE initialization is started 0x71 South Br...

Page 93: ...0xA3 IDE Enable 0xA4 SCSI initialization is started 0xA5 SCSI Reset 0xA6 SCSI Detect 0xA7 SCSI Enable 0xA8 Setup Verifying Password 0xA9 Start of Setup 0xAA Reserved for ASL see ASL Status Codes secti...

Page 94: ...rror loading Boot Option LoadImage returned error 0xDA Boot Option is failed StartImage returned error 0xDB Flash update is failed 0xDC Reset protocol is not available 8 2 6 DXE Beep Codes of Beeps De...

Page 95: ...ansitioned into ACPI mode Interrupt controller is in PIC mode 0xAA System has transitioned into ACPI mode Interrupt controller is in APIC mode 8 3 OEM Reserved Checkpoint Ranges Status Code Descriptio...

Page 96: ...90 BIOS Checkpoints Beep Codes This page intentionally left blank...

Page 97: ...should be free of components Tyco 3 6318491 6 Foxconn QT002206 4141 3H ePT 401 55103 51 220 pin board to board connector with 0 5mm for a stacking height of 8 mm This connector can be used with 8 mm t...

Page 98: ...dule is compatible with all COM Express modules 9 2 2 Heat Sinks A heat sink can be used as a thermal solution for a specific COM Express module and can have a fan or be fanless depending on the therm...

Page 99: ...module Step 5 Place the COM Express module and heatsink assembly onto the connectors on the carrier board as shown Then press down on the module until it is firmly seated on the carrier board Step 6...

Page 100: ...94 Mechanical Information Step 7 If you are installing a heatsink with a fan plug the fan connector into the carrier board as shown...

Page 101: ...o a carrier board There is the choice of Top and Bottom mounting In Top mounting the threaded standoffs are on the carrier board and the thermal solution is equipped with through hole standoffs In Bot...

Page 102: ...g methods are shown below Note that threaded standoffs are DIP type and through hole standoffs are SMT type Other types not listed are available upon request 8mm through hole standoff SMT type P N 33...

Page 103: ...bles To avoid electrical shock and or damage to equipment Keep equipment away from water or liquid sources Keep equipment away from high heat or high humidity Keep equipment properly ventilated do not...

Page 104: ...200 Toll Free 1 800 966 5200 USA only Fax 1 408 360 0222 Email info adlinktech com ADLINK Technology China Co Ltd Address 300 Fang Chun Rd Zhangjiang Hi Tech Park Pudong New Area Shanghai 201203 China...

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