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••

8254 Programmable Interval Time

A.2 The Control Byte

The 8254 occupies 8 I/O address locations in the PCI-7200 I/O
map. As shown below.

Base + 0

LSB OR MSB OF COUNTER 0

Base + 4

LSB OR MSB OF COUNTER 1

Base + 8

LSB OR MSB OF COUNTER 2

Base + C

CONTROL BYTE for Chip 0

Before loading or reading any of these individual counters, the

control byte

(Base + C

)

must be loaded first. The format of control

byte is :

Control Byte : (

Base + 7, Base + 11)

Bit

SC1

SC0

RL1

RL0

BCD

•

SC1 & SC1 - Select Counter (Bit7 & Bit 6)

SC1

SC0

COUNTER

ILLEGAL

•

RL1 & RL0 - Select Read/Load operation (Bit 5 & Bit 4)

RL1

RL0

OPERATION

COUNTER LATCH

READ/LOAD LSB

READ/LOAD MSB

READ/LOAD LSB FIRST, THEN MSB

Summary of Contents for cPCI-7200

Page 1: ...PCI 7200 cPCI 7200 12MB S High Speed Digital Input Output Card ...

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Page 3: ... out of the use or inability to use the product or documentation even if advised of the possibility of such damages This document contains proprietary information protected by copyright All rights are reserved No part of this manual may be reproduced by any mechanical electronic or other means in any form without prior written permission of the manufacturer Trademarks PCI 7200 and cPCI 7200 are re...

Page 4: ...ne 10 2 5 1 Hardware configuration 10 2 5 2 Slot selection 10 2 5 3 Installation Procedure 10 2 5 4 Running the 7200UTIL EXE 11 2 6 Connector Pin Assignment 11 2 6 1 PCI 7200 Pin Assignment 11 2 6 2 cPCI 7200 Pin Assignment 13 2 7 8254 for Timer Pacer Generation 13 CHAPTER 3 Register Structure Format 15 3 1 I O Registers Format 15 3 2 Digital Input Register BASE 10 16 3 3 Digital Output Register B...

Page 5: ...5 5 _7200_Switch_Card_No 38 5 6 _7200_AUX_DI 39 5 7 _7200_AUX_DI_Channel 40 5 8 _7200_AUX_DO 41 5 9 _7200_AUX_DO_Channel 42 5 10 _7200_DI 43 5 11 _7200_DI_Channel 44 5 12 _7200_DO 45 5 13 _7200_DO_Channel 46 5 14 _7200_Alloc_DMA_Mem 47 5 15 _7200_Free_DMA_Mem 49 5 16 _7200_Alloc_DBDMA_Mem 50 5 17 _7200_Free_DBDMA_Mem 51 5 18 _7200_DI_DMA_Start 52 5 19 _7200_DI_DMA_Status 56 5 20 _7200_DI_DMA_Stop ...

Page 6: ...p 65 5 28 _7200_DI_Timer 66 5 29 _7200_DO_Timer 68 CHAPTER 6 Double Buffer Mode Principle 71 CHAPTER 7 Limitation 73 Appendix A 8254 Programmable Interval Timer 75 A 1 The Intel NEC 8254 75 A 2 The Control Byte 76 A 3 Mode Definition 77 Product Warranty Service 81 ...

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Page 8: ...ation describes how to install the PCI 7200 The layout of PCI 7200 is shown and the installation procedures pin assignment of connectors and timer pacer generation are specified Chapter 3 Register Structure Format describes the low level register structure and format of the PCI 7200 Chapter 4 Operation Theorem describes how the PCI 7200 works Chapter 5 C C DLL Library describes the high level C an...

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Page 10: ...MB per second It is very suitable for interface between high speed peripherals and your computer system Several different digital I O operation modes are supported 1 Direct Program Control the digital inputs and outputs can be accessed and controlled by its corresponding I O ports directly 2 Timer Pacer Mode the digital input and output operations are handled by internal timer pacer clock and tran...

Page 11: ... Applications Interface to high speed peripherals High speed data transfers from other computers Digital I O control Interface to external high speed A D and D A converter Digital pattern generator Waveform and pulse generation BCD interface driver 1 2 Features The PCI 7200 high speed DIO Card provides the following advanced features 32 TTL digital input channels 32 TTL digital output channels Tra...

Page 12: ... Input Load Low 0 5V 0 6mA max High 2 7V 20µA max Output Voltage Low Min 0V Max 0 5V High Min 2 7V Driving Capacity Low Max 0 5V at 24mA Sink High Min 2 4V at 3 0mA Source Auxiliary Digital I O AUXDIO Channel 4 TTL compatible inputs and outputs Device TTL74F244 Programmable Counter Device 82C54 10 Timer Pacer 16 bit 32 bit timer two 16 bit counter cascaded together with a 4MHz time base Counter On...

Page 13: ...Connector PCI 7200 one 37 pin D type and one 40 pin ribbon connector cPCI 7200 one 100 pin SCSI type connector Dimension PCI 7200 Compact size only 98mm H X 147mm L cPCI 7200 Standard 3U CompactPCI form factor Power Consumption PCI 7200 5 V 500 mA max cPCI 7200 5 V 600 mA max ...

Page 14: ...dress are assigned by the system BIOS during system boot up 2 1 What You Have In addition to this User s Manual the package includes the following items PCI 7200 Digital I O Counter Card include ACL 10437 40 pin to 37 pin D Sub cable or cPCI 7200 Digital I O Counter Card include 100 pin SCSI connector assembly Manual Software Utility CD If any of these items is missing or damaged contact the deale...

Page 15: ... before processing After opening the card module carton extract the system module and place it only on a grounded anti static surface component side up Again inspect the module for damage Press down on all the socketed IC s to make sure that they are properly seated Do this only with the module place on a firm flat surface Note DO NOT APPLY POWER TO THE CARD IF IT HAS BEEN DAMAGED You are now read...

Page 16: ...en a dialog box is shown to prompt you give the path of installation disk Place ADLink s Manual Software Utility CD into the appropriate CD driver Type X Software NuDAQPCI 7200 Win95 in the input field X indicates the CD ROM driver and then click OK The system will start the installation of PCI 7200 ...

Page 17: ...8 Installation 2 4 PCI 7200 s Layout CN1 PCI 7200 Rev A1 CN2 ALTERA PCI Bus Controller Figure 2 1 PCI 7200 Layout Diagram ...

Page 18: ...Installation 9 Figure 2 1a PCI 7200 Layout Diagram ...

Page 19: ... to computer 3 Remove the cover from your computer 4 Select a 32 bit PCI expansion slot for PCI 7200 or CompactPCI peripheral slot for cPCI 7200 PCI slots are short than ISA or EISA slots and are usually white or ivory CompactPCI peripheral slots are marked with a circle on the backplane Caution Don t put PCI 7200 card into ISA or EISA slot 5 Before handling the PCI 7200 discharge any static build...

Page 20: ...ed on the rear mounting plate and one 40 pin female flat cable header connector CN1 The CN2 is located on the rear mounting plate the CN1 is on front of the board Refer section 2 2 PCI 7200 s layout CN2 is used for digital inputs DI 0 DI 15 and digital outputs DO 0 DO 15 and the reminder digital I O channels DI 16 DI 31 and DO 16 DO 31 are presented on the CN1 The pin assignment of CN1 and CN2 is ...

Page 21: ...26 DI 22 DI 27 DO19 DO20 DO28 DO29 DO30 DO 31 DO21 DO23 DO24 DO25 DO26 DO22 DO27 DO17 DO18 N C N C N C Figure 2 2 CN1 Pin Assignment 1 2 3 4 5 6 10 11 12 13 14 15 7 8 9 16 17 18 19 20 21 22 23 24 25 26 27 28 30 31 32 33 29 35 36 37 34 DI 1 DI 2 DI 3 DI 4 DI 5 DI 6 DI 7 DI 8 DI10 DO10 DO11 DO12 DO13 DO14 DO15 DI 9 GND I_TRG DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 DO8 DO9 DI 0 DI11 DI12 DI13 DI14 DI15 5V I_...

Page 22: ...3 6 DO10 31 5Vout 56 DO11 81 GND 7 DO12 32 5Vout 57 DO13 82 GND 8 DO14 33 GND 58 DO15 83 GND 9 GND 34 DIN0 59 GND 84 DIN1 10 DO16 35 DIN2 60 DO17 85 DIN3 11 DO18 36 DIN4 61 DO19 86 DIN5 12 DO20 37 DIN6 62 DO21 87 DIN7 13 DO22 38 DIN8 63 DO23 88 DIN9 14 DO24 39 DIN10 64 DO25 89 DIN11 15 DO26 40 DIN12 65 DO27 90 DIN13 16 DO28 41 DIN14 66 DO29 91 DIN15 17 DO30 42 GND 67 DO31 92 GND 18 GND 43 DIN16 68...

Page 23: ...2 can be cascaded together to generate more timer pacer frequency for digital input Also the Timer 2 can be cascaded with Timer 1 for digital output pacer rate 4 MHz C0 C2 if Timer 0 Timer 2 are cascaded pacer rate 4 MHz C0 if timer 0 Timer 2 are not cascaded The maximum pacer signal rate of input and output are 4MHz 2 2Mhz The minimum signal rate is 4MHz 65535 65535 which is a very slow frequency...

Page 24: ...4 1 shows the I O Map Address Read Write Base 0 Counter 0 Counter 0 Base 4 Counter 1 Counter 1 Base 8 Counter 2 Counter 2 Base C CLK Control CW0 Base 10 Digital Input Reg Base 14 Digital Output Read back Digital Output Reg Base 18 DIO Status Control DIO Status Control Base 1C INT Status Control INT Status Control Base 20 cPCI 7200 only AUXDIO Reg AUXDO Reg Caution 1 I O port is 32 bit width 2 8 bi...

Page 25: ... DI19 DI18 DI17 DI16 Base 13 DI31 DI30 DI29 DI28 DI27 DI26 DI25 DI24 3 3 Digital Output Register BASE 14 32 digital output channels can be write and read back from this register Address BASE 14 Attribute READ WRITE Data Format Byte 7 6 5 4 3 2 1 0 Base 14 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 Base 15 DO15 DO14 DO13 DO12 DO11 DO10 DO9 DO8 Base 16 DO23 DO22 DO21 DO20 DO19 DO18 DO17 DO16 Base 17 DO31 DO30 ...

Page 26: ...20 O_UND Base 21 Digital Input Mode Setting I_ACK Input ACK Enable 1 Input ACK is enabled input ACK will be asserted after input data is read by CPU or written to input FIFO 0 Input ACK is disabled I_REQ Input REQ Strobe Enabled 1 Use I_REQ edge to latch input data 0 I_REQ is disabled I_TIME0 Input Timer 0 Enable 1 Input is sampled by falling edge of Counter 0 output COUT0 0 Input Timer 0 is disab...

Page 27: ...put operation will be stopped Digital Output Mode Setting O_ACK Output ACK Enable 1 Output ACK is enabled the output circuit will wait for O_ACK after O_REQ strobe is asserted 0 Output ACK is disabled O_REQ Output REQ Enable 1 Output REQ is enabled an O_REQ strobe will be generated after output data is ready 0 Output REQ is disabled O_TIME1 Output Timer 1 Enable 1 Output Timer 1 is enabled output ...

Page 28: ...here is new input data coming in This bit can be cleared by writing 1 to it O_UND Output data FIFO is underrun 1 Output FIFO is empty during output data trancfer 0 No output data underrun occurred Output data underrun the O_UND bit is set when output FIFO is empty and the output request for new data this bit can be cleared by writing 1 to it 3 5 Interrupt Status Control Register BASE 1C The interr...

Page 29: ...led 0 I_REQ interrupt is disabled T0_EN Interrupt is triggered by timer 0 output 1 Timer 0 interrupt is enabled 0 Timer 0 interrupt is disabled T1_EN Interrupt is triggered by timer 1 output 1 Timer 1 interrupt is enabled 0 Timer 1 interrupt is disabled T2_EN Interrupt is triggered by timer 2 output 1 Timer 2 interrupt is enabled 0 Timer 2 interrupt is disabled Interrupt Status The following bits ...

Page 30: ...e routine has to clear all the interrupt status before end of the ISR Timer Configuration Control The 8254 timer on the PCI 7200 can be configured as either timer 0 cascaded with timer 2 or timer 1 cascaded with timer2 These configuration are controlled by the following bits T0_T2 Timer 0 is cascaded with timer 2 1 Timer 0 and timer 2 are cascaded together output of timer 2 connects to the clock i...

Page 31: ...gital input FIFO The FIFO can be cleared and monitored by the following bits FIFORST Write only Clear the on board DI FIFO 1 Write 1 to clear the data of the FIFO 0 No operation FIFOEF Read only Empty flag of the DI FIFO 1 DI FIFO is empty 0 DI FIFO is not empty FIFOFF Read only Full flag of the DI FIFO 1 DI FIFO is full 0 DI FIFO is not full Note The cPCI 7200 has 2 cascaded DI FIFOs One is locat...

Page 32: ...rations are paced by internal timer pacer and transferred by bus mastering DMA 3 External Clock Mode the digital input operation is clocked by external I_REQ strobe and transferred by bus mastering DMA 4 Handshaking through REQ and ACK signals the digital I O can have simple handshaking data transfer 4 1 Direct Program Control The digital I O operations can be controlled by I O port BASE 10 for di...

Page 33: ...is clocked by timer pacer which is generated by a interval programming timer counter chip 8254 There are three timers on the 8254 The timer 0 is used to generate timer pacer for digital input and timer 1 is used for digital output The configuration is illustrated as below Timer 0 Timer 1 Timer 2 CLK0 GATE0 OUT0 CLK1 GATE1 CLK2 GATE2 OUT1 OUT2 8254 Timer Counter Digital Input Timer Pacer Digital Ou...

Page 34: ...cer 3 The data saved in FIFO will be transferred to main memory of your computer system directly and automatically This is controlled by bus mastering DMA control this function is supported by PCI controller chip The operation flow is show as below Timer 0 CLK0 GATE0 OUT0 8254 Timer Counter To Digital Input Trigger Latch Digital Input Digital Input FIFO Bus mastering DMA data Transfer PC s Main Me...

Page 35: ...generated from outside device and go through the Pin 19 I_REQ of CN2 and to latch the digital input 2 The digital input data are saved in FIFO after an I O strobe signal is coming in 3 The data saved in input FIFO will be transferred to main memory on your computer system directly This is controlled by bus mastering DMA control this function is supported by PCI To Digital Input Trigger Latch Digit...

Page 36: ...CK for Digital Input 1 Digital Input Data is ready 2 An I_REQ signal is generated for digital input operation 3 Digital input data is saved to FIFO 4 An I_ACK signal is generated and sent to outside device 5 If the FIFO is not empty and PCI bus is not occupied the data will be transferred to main memory Latch Digital Input or Digital Output Digital Input FIFO Bus mastering DMA data Transfer PC s M...

Page 37: ...al output circuit 3 Output data is ready 4 An O_REQ signal is generated and sent to outside device 5 After an O_ACK is got the step 2 to step 5 will be repeated again If the FIFO is not full the output data is moved form PC s main memory to FIFO automatically O_REQ O_ACK Move Data to Digital Output FIFO Bus mastering DMA data Transfer PC s Main Memory 2 4 3 1 Digital Output DATA 5 Digital Output ...

Page 38: ...ge Active IN_REQ th tl tcyc valid data valid data ts tn DI0 DI31 t h 60ns tl 60ns ts 2ns tn 30ns tcyc 5 PCI CLK Cycle 2 I_REQ as input data strobe Falling Edge Active IN_REQ th tl tcyc valid data valid data ts tn DI0 DI31 t h 60ns tl 60ns ts 2ns tn 30ns tcyc 5 PCI CLK Cycle I_REQ I_REQ ...

Page 39: ...Q t 1 t2 t3 valid data valid data t5 t4 DI0 DI31 t1 0ns t5 60ns t2 0ns t4 t3 2 PCI CLK Cycle IN_ACK 1 PCI CLK Cycle 4 O_REQ as output data strobe OUT_REQ th tcyc valid data valid data ts D00 D031 t s 19ns th 500ns tcyc 2 PCI CLK Cycles I_REQ I_ACK O_REQ ...

Page 40: ...t1 t3 valid data DO0 Do31 t1 19ns t3 t2 1 PCI CLK Cycle OUT_ACK 5 PCI CLK Cycle valid data t2 Note O_ACK must be de asserted before O_REQ asserts O_ACK can be asserted any time after O_REQ asserts O_REQ will be reasserted after O_ACK is asserted O_REQ O_ACK ...

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Page 42: ... library DLL libraries and some demonstration programs which can help you reduce programming work MS DOS Installation 1 Turn your PC s power switch on 2 Put the ADLink s All in one CD into the appropriate CD drive 3 Type the command X indicates the CD ROM drive X CD NUDAQPCI 7200 DOS X NUDAQPCI 7200 DOS SETUP 4 An installation complete message will be shown on the screen After installation all the...

Page 43: ...g dialog box for you to specify the destination directory The default path is C ADLink 7200 W95 If you want to install PCI 7200 DLL for Windows 95 in another directory please click Browse button to change the destination directory Then you can click Next to begin installing PCI 7200 DLL for Windows 95 After you complete the installation of PCI 7200 Software PCI 7200 s DLL 7200 DLL is copied to Win...

Page 44: ...ll be displayed on you screen You can test the functionality 1 Digital I O in polling mode Direct Program Control 2 Digital I O DMA mode Timer Pacer Trigger and Bus Mastering DMA data transfer 3 AUX Digital I O for cPCI 7200 only PCI 7200 Utility Rev 1 10 Copyright 1995 1999 ADLink Technology Inc All rights reserved F1 DIO Polling Mode Testing F2 DIO DMA Mode Testing F3 AUX DIO Testing cPCI 7200 o...

Page 45: ...ion calls provided by each driver for PCI 7200 Digital I O cards all drivers DOS Win 95 98 provide the same function capability The function names using in Windows is only a capital W put on the head of each function name of DOS library The detailed descriptions of each function are specified in the following sections 5 4 _7200_Initial Description A PCI 7200 card is initialized according to the ca...

Page 46: ...mber U16 base_addresss U8 irq_no Argument card_number the card number to be initialized only four cards can be initialized the card number must be CARD_1 CARD_2 CARD_3 or CARD_4 base_address the I O port base address of the card it is assigned by system BIOS irq_no system will give an available interrupt number to this card automatically Return Code ERR_NoError ERR_InvalidBoardNumber ERR_PCIBiosNo...

Page 47: ...95 98 int W_7200_Switch_Card_No U8 card_number Visual Basic Windows 95 98 W_7200_Switch_Card_No ByVal card_number As Byte As Long C C DOS int _7200_Switch_Card_No U8 card_number Argument card_number The card number to be initialized four cards can be initialized the card number must be CARD_1 CARD_2 CARD_3 or CARD_4 but only one card is active Return Code ERR_NoError ERR_InvalidBoardNoInit ...

Page 48: ...n get all 4 bits input data by using this function Syntax Visual C Windows 95 98 int W_7200_AUX_DI U32 aux_di Visual Basic Windows 95 98 W_7200_DI aux_di As Long As Long C C DOS int _7200_DI U32 aux_di Argument aux_di returns 4 bit value from auxiliary digital input port Return Code ERR_NoError ERR_FunctionNotAvailable ...

Page 49: ...ponding channel is returned channel means each bit of digital input port Syntax Visual C Windows 95 98 int W_7200_AUX_DI_Channel U8 di_ch_no Boolean aux_data Visual Basic Windows 95 98 W_7200_AUX_DI_Channel ByVal di_ch_no As Byte aux_data As Byte As Long C C DOS int _7200_AUX_DI_Channel U8 di_ch_no Boolean aux_data Argument di_ch_no the DI channel number the value has to be set within 0 and 3 aux_...

Page 50: ...digital outputs on the cPCI 7200 Syntax Visual C Windows 95 98 int W_7200_AUX_DO U32 aux_do Visual Basic Windows 95 98 W_7200_AUX_DO ByVal aux_do As Long As Long C C DOS int _7200_AUX_DO U32 aux_do Argument aux_do value will be written to auxiliary digital output port Return Code ERR_NoError ERR_FunctionNotAvailable ...

Page 51: ...means each bit of digital input port Syntax Visual C Windows 95 98 int W_7200_AUX_DO_Channel U8 do_ch_no Boolean aux_data Visual Basic Windows 95 98 W_7200_AUX_DO_Channel ByVal do_ch_no As Byte ByVal aux_data As Byte As Long C C DOS int _7200_AUX_DO_Channel U8 do_ch_no Boolean aux_data Argument do_ch_no the auxiliary DO channel number the value has to be set within 0 and 3 aux_data either 0 OFF or...

Page 52: ...ital inputs on the PCI 7200 You can get all 32 input data from _7200_DI by using this function Syntax Visual C Windows 95 98 int W_7200_DI U32 di_data Visual Basic Windows 95 98 W_7200_DI di_data As Long As Long C C DOS int _7200_DI U32 di_data Argument di_data returns all 32 bit value from digital port Return Code ERR_NoError ...

Page 53: ...ponding channel is returned channel means each bit of digital input port Syntax Visual C Windows 95 98 int W_7200_DI_Channel U8 di_ch_no Boolean di_data Visual Basic Windows 95 98 W_7200_DI_Channel ByVal di_ch_no As Byte di_data As Byte As Long C C DOS int _7200_DI_Channel U8 di_ch_no Boolean di_data Argument di_ch_no the DI channel number the value has to be set within 0 and 31 di_data return val...

Page 54: ...utput port There are 32 digital outputs on the PCI 7200 Syntax Visual C Windows 95 98 int W_7200_DO U32 do_data Visual Basic Windows 95 98 W_7200_DO ByVal do_data As Long As Long C C DOS int _7200_DO U32 do_data Argument do_data value will be written to digital output port Return Code ERR_NoError ...

Page 55: ...sponding channel l channel means each bit of digital input port Syntax Visual C Windows 95 98 int W_7200_DO_Channel U8 do_ch_no Boolean do_data Visual Basic Windows 95 98 W_7200_DO_Channel ByVal do_ch_no As Byte ByVal do_data As Byte As Long C C DOS int _7200_DO_Channel U8 do_ch_no Boolean do_data Argument do_ch_no the DO channel number the value has to be set within 0 and 31 do_data either 0 OFF ...

Page 56: ...size As Long As Long Argument buff The start address of the user buffer for DMA data transfer This buffer will be attached to the DMA memory allocated by this function When using this DMA memory handle as an argument of W_7200_DI_DMA_Start function DI data will be copied to this buffer When using this DMA memory handle as an argument of W_7200_DO_DMA_Start function the data stored in this buffer w...

Page 57: ...ystem is not able to get a block of contiguous memory of specified buf_size it will allocate a block of memory as large as it can In this case this function returns ERR_SmallerDMAMemAllocated and actual_size denotes the actual size of allocated memory Return Code ERR_NoError ERR_SmallerDMAMemAllocated ...

Page 58: ... 95 98 environment This function is only available in Windows 95 98 version Syntax Visual C Windows 95 98 int W_7200_Free_DMA_Mem U32 handle Visual Basic Windows 95 98 W_7200_Free_DMA_Mem ByVal handle As Long As Long Argument handle The handle of system DMA memory to deallocate Return Code ERR_NoError ...

Page 59: ...he is a dummy buffer attached to the DMA memory this function will allocate But this buffer need to have size equal to or more than buf_size bytes handle The handle of system DMA memory returned from system Use this handle in _7200_DI_DMA_Start buf_size Bytes to allocate This is the half size of circular buffer in byte That is this is the size of each half buffer in byte actual_size The actual DMA...

Page 60: ...available in Windows 95 98 version For double buffered transfer principle please refer to Section 6 Double Buffered Mode Principle Syntax Visual C Windows 95 98 int W_7200_Free_DBDMA_Mem U32 handle Visual Basic Windows 95 98 W_7200_Free_DBDMA_Mem ByVal handle As Long As Long Argument handle The handle of system DMA memory to deallocate Return Code ERR_NoError ...

Page 61: ...A Its description is as follow Bus Mastering DMA mode of PCI 7200 PCI bus mastering offers the highest possible speed available on the PCI 7200 When the function _7200_DI_DMA_Start is executed it will enable PCI bus master operation This is conceptually similar to DMA Direct Memory Access transfers in a PC but is really PCI bus mastering It does not use an 8237 style DMA controller in the host com...

Page 62: ... PCI 7200 will relinquish the bus temporarily but returns immediately when more input data appear This operation continues until the whole block is done 4 This operation proceeds transparently until the PCI controller transfer byte count is reached All normal PCI bus operation applies here such as a receiver which cannot accept the transfers higher priority devices requesting the PCI bus etc Remem...

Page 63: ...r_fifo Boolean disable_di Argument mode Digital Input trigger modes DI_MODE0 Internal timer pacer TIME 0 DI_MODE1 external signal I_REQ rising edge DI_MODE2 external signal I_REQ falling edge DI_MODE3 I_REQ I_ACK handshaking count For non double buffered DI this parameter denotes the number of digital input samples to read For double buffered DI it is the size of circular buffer in samples not in ...

Page 64: ... alignment wait_trig The waiting status of trigger DI_NONWAITING the input sampling will be start immediately DI_WAITING the input samples waiting rising or falling edge trigger to start DI trig_pol trigger polarity DI_RISING rising edge trigger DI_FALLING falling edge trigger clear_fifo 0 retain the FIFO data 1 clear FIFO data before perform digital input disable_di 0 digital input operation stil...

Page 65: ... mode is set as disable Syntax Visual C Windows 95 98 int W_7200_DI_DMA_Status U8 status U32 count Visual Basic Windows 95 98 W_7200_AD_Status status As Byte count As Long As Long C C DOS int _7200_AD_DMA_Status U8 status U32 count Argument status status of the DMA data transfer 0 DI_DMA_STOP DMA is completed 1 DI_DMA_RUN DMA is not completed count the numbers of DI data which has been transferred...

Page 66: ... the data which has been transferred no matter if the digital input DMA data transfer is stopped by this function or by the DMA terminal count ISR Syntax Visual C Windows 95 98 int W_7200_DI_DMA_Stop U32 count Visual Basic Windows 95 98 W_7200_DI_DMA_Stop count As Long As Long C C DOS int _7200_DI_DMA_Stop U32 count Argument count the number of DI data which has been transferred Return Code ERR_No...

Page 67: ...e for DMA DI operation Syntax Visual C Windows 95 98 int W_7200_DblBufferMode Boolean db_flag Visual Basic Windows 95 98 W_7200_DblBufferMode ByVal db_flag As Byte As Long C C DOS int _7200_CheckHalfReady Boolean db_flag Argument db_flag 1 double buffer mode enabled 0 double buffer mode disabled Return Code ERR_NoError ...

Page 68: ...ckHalfReady to check data ready data half full or not in the circular buffer and using _7200_DblBufferTransfer to get data Syntax Visual C Windows 95 98 int W_7200_CheckHalfReady Boolean halfReady Visual Basic Windows 95 98 W_7200_CheckHalfReady halfReady As Byte As Long C C DOS int _7200_CheckHalfReady Booelan halfReady Argument halfReady 1 TRUE or 0 FALSE Return Code ERR_NoError ...

Page 69: ... half to the transfer buffer Syntax Visual C Windows 95 98 int W_7200_DblBufferTransfer U32 userBuffer Visual Basic Windows 95 98 W_7200_DblBufferTransfer userBuffer As Long As Long C C DOS int _7200_DblBufferTransfer U32 userBuffer Argument userBuffer the start address of the transfer buffer W_7200_DblBufferTransfer function copies half of the circular buffer to userBuffer Return Code ERR_NoError...

Page 70: ...nsfer to move converted data then the double buffer overrun will occur using this function to check overrun count Syntax Visual C Windows 95 98 int W_7200_GetOverrunStatus U32 overrunCount Visual Basic Windows 95 98 int W_7200_GetOverrunStatus overrunCount As Long As Long C C DOS int _7200_GetOverrunStatus U32 overrunCount Argument overrunCount number of overrun counts Return Code ERR_NoError ...

Page 71: ...r executing this function it is necessary to check the status of the operation by using the function _7200_DO_DMA_Status Syntax Visual C Windows 95 98 int W_7200_DO_DMA_Start U8 mode U32 count U32 handle Boolean repeat Visual Basic Windows 95 98 W_7200_DO_DMA_Start ByVal mode As Byte ByVal count As Long ByVal handle As Long ByVal repeat as Byte As Long C C DOS int _7200_DO_DMA_Start U8 mode U32 co...

Page 72: ... data is stored in the buffer attached to this handle do_buffer DOS the start address of the memory buffer to store the DO data This memory should be double word alignment repeat The digital output will be continuous or only one shot CONTINUOUS digital output will be continuous until the _7200_DO_DMA_STOP is called ONE_SHOT digital output only one shot Return Code ERR_NoError ERR_InvalidDIMode ERR...

Page 73: ...Syntax Visual C Windows 95 98 int W_7200_DO_DMA_Status U8 status U32 count Visual Basic Windows 95 98 W_7200_DO_Status status As Byte count As Long As Long C C DOS int _7200_DO_DMA_Status U8 status U32 count Argument status status of the DMA data transfer 0 DO_DMA_STOP DMA is completed 1 DO_DMA_RUN DMA is not completed count the numbers of DO data which has been transferred Return Code ERR_NoError...

Page 74: ... which has been transferred no matter if the digital output DMA data transfer is stopped by this function or by the DMA terminal count ISR Syntax Visual C Windows 95 98 int W_7200_DO_DMA_Stop U32 count Visual Basic Windows 95 98 W_7200_DO_DMA_Stop count As Long As Long C C DOS int _7200_DO_DMA_Stop U32 count Argument count the number of digital output data which has been transferred Return Code ER...

Page 75: ...nter 4MHz Input Digital Input Trigger Timer pacer frequency 4Mhz C0 2 Cascaded TIME2 cascaded with COUNTER0 Counter 0 Counter 1 Counter 2 CLK0 GATE0 OUT0 CLK1 GATE1 CLK2 GATE2 OUT1 OUT2 8254 Timer Counter 4MHz Input Digital Input Trigger Timer pacer frequency 4Mhz C0 C2 Syntax Visual C Windows 95 98 int W_7200_DI_Timer U16 c0 U16 c2 Boolean mode Visual Basic Windows 95 98 W_7200_DI_Timer ByVal c0 ...

Page 76: ...ode Argument c0 frequency divider of Counter 0 Valid value ranges from 2 to 65535 c2 frequency divider of Counter 2 Valid value ranges from 2 to 65535 mode TIMER_NONCASCADE or TIMER_CASCADE Return Code ERR_NoError ERR_InvalidBoardNumber ERR_InvalidTimerMode ERR_BoardNoInit ...

Page 77: ...nter 4MHz Input Digital Output Trigger Timer pacer frequency 4Mhz C1 2 Cascaded TIME2 cascaded with COUNTER0 Counter 0 Counter 1 Counter 2 CLK0 GATE0 OUT0 CLK1 GATE1 CLK2 GATE2 OUT1 OUT2 8254 Timer Counter 4MHz Input Digital Input Trigger Timer pacer frequency 4Mhz C1 C2 Syntax Visual C Windows 95 98 int W_7200_DO_Timer U16 c1 U16 c2 Booelan mode Visual Basic Windows 95 98 W_7200_DO_Timer ByVal c1...

Page 78: ...00_DO_Timer U16 c1 U16 c2 Boolean mode Argument c1 frequency divider of Counter 1 c2 frequency divider of Counter 2 mode TIMER_NONCASCADE or TIMER_CASCADE Return Code ERR_NoError ERR_InvalidBoardNumber ERR_InvalidTimerMode ERR_BoardNoInit ...

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Page 80: ...r buffer you can copy the data from the first half into the transfer buffer Figure 6 1b You now can process the data in the transfer buffer according to application needs After the board has filled the second half of the circular buffer the board returns to the first half buffer and overwrites the old data You now can copy the second half of the circular buffer to the transfer buffer Figure 6 1c T...

Page 81: ...00_CheckHalfReady to check if data in the circular buffer is half full and ready for copying to the transfer buffer Then you can call _7200_DblBufferTransfer to copy data from the ready half buffer to the transfer buffer In Win 95 version W_7200_Alloc_DBDMA_Mem is needed to allocates a contiguous DMA memory for the circular buffer The buf_size argument of W_7200_Alloc_DBDMA_Mem is the half size of...

Page 82: ...st two modes cannot guarantee the input data integrity in high speed data rate because of the limited FIFO depth and the PCI bus latency variation The handshaking mode is the only mode that data integrity can be guaranteed In handshaking mode you can expect 12 MB sec data rate in average but the speed is not guaranteed 3 The guaranteed data rate with internal clock or external clock mode is 1MB se...

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Page 84: ...e independent 16 bit counters can be clocked at rates from DC to 5 MHz Each counter can be individually programmed with 6 different operating modes by appropriately formatted control words The most commonly uses for the 8254 in microprocessor based system are programmable baud rate generator event counter binary rate multiplier real time clock digital one shot motor control For more information ab...

Page 85: ...or Chip 0 Before loading or reading any of these individual counters the control byte Base C must be loaded first The format of control byte is Control Byte Base 7 Base 11 Bit 7 6 5 4 3 2 1 0 SC1 SC0 RL1 RL0 M2 M1 M0 BCD SC1 SC1 Select Counter Bit7 Bit 6 SC1 SC0 COUNTER 0 0 0 0 1 1 1 0 2 1 1 ILLEGAL RL1 RL0 Select Read Load operation Bit 5 Bit 4 RL1 RL0 OPERATION 0 0 COUNTER LATCH 0 1 READ LOAD LS...

Page 86: ...om 0 up to 99 999 A 3 Mode Definition In 8254 there are six different operating modes can be selected The they are Mode 0 interrupt on terminal count The output will be initially low after the mode set operation After the count is loaded into the selected count register the output will remain low and the counter will count When terminal count is reached the output will go high and remain high unti...

Page 87: ...ggerable hence the output will remain low for the full count after any rising edge of the gate input Mode 2 Rate Generator Divided by N counter The output will be low for one period of the input clock The period from one output pulse to the next equals the number of input counts in the count register If the count register is reloaded between output pulses the present period will not be affected bu...

Page 88: ...ime out the output goes low and the full count is reloaded The first clock pulse following the reload decrements the counter by 3 Subsequent clock pulses decrement the count by 2 until time out Then the whole process is repeated In this way if the count is odd the output will be high for N 1 2 counts and low for N 1 2 counts In Modes 2 and 3 if a CLK source other then the system clock is used GATE...

Page 89: ...ng edge of the trigger input and will go low for one clock period when the terminal count is reached The counter is re triggerable the output will not go low until the full count after the rising edge of any trigger The detailed description of the mode of 8254 please refer the Intel Microsystem Components Handbook ...

Page 90: ...g its specifications or if the serial number has been removed Seller does not assume any liability for consequential damages as a result from our products uses and in any event our liability shall not exceed the original selling price of the equipment The equipment warranty shall constitute the sole and exclusive remedy of any Buyer of Seller equipment and the sole and exclusive liability of the S...

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