nanoX-BT
Page 35
6.3.
Interrupt Request (IRQ) Lines
6.3.1.
PIC Mode
IRQ#
Typical Intterupt Resource
Connected to Pin
Available
0 Counter
0
N/A
No
1
Keyboard controller
IRQ1 via SERIRQ / PIRQ
No
2
Cascade interrupt from slave PIC
N/A
No
3
Generic
IRQ3 via SERIRQ / PIRQ
Note (1)
4
PCU Serial Port (COM1)
IRQ4 via SERIRQ / PIRQ
Note (1)
5
Generic
IRQ5 via SERIRQ / PIRQ
Note (1)
6
Generic
IRQ6 via SERIRQ / PIRQ
Note (1)
7
Generic
IRQ7 via SERIRQ / PIRQ
Note (1)
8 Real-time
clock
N/A
No
9
Generic
IRQ9 via SERIRQ / PIRQ
Note (1)
10
Generic
IRQ10 via SERIRQ / PIRQ
Note (1)
11
Generic
IRQ11 via SERIRQ / PIRQ
Note (1)
12
Generic
IRQ12 via SERIRQ / PIRQ
Note (1)
13 Math
Processor
N/A
No
14
Primary IDE controller
IRQ14 via SERIRQ / PIRQ
Note (1)
15
Secondary IDE controller
IRQ15 via SERIRQ / PIRQ
Note (1)
Note (1):
These IRQs can be used for PCI devices when onboard device is disabled.
6.3.2.
APIC Mode
IRQ#
Typical Intterupt Resource
Connected to Pin
Available
0 System
timer
N/A
No
1 N/A
N/A
No
2 N/A
N/A
No
3 N/A
N/A
Note
(1)
4
Serial Port 1 (COM1)
IRQ4 via SERIRQ / PIRQ
Note (1)
5 N/A
N/A
Note
(1)
6 N/A
N/A
Note
(1)
7 N/A
N/A
Note
(1)
8
High precision event timer
N/A
No
9 N/A
N/A
Note
(1)
10 N/A
N/A
Note
(1)
11 N/A
N/A
Note
(1)
