ADLINK Technology Com Express nanoX-BT User Manual Download

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Page 2

nanoX-BT

Revision History

Revision

Description

Date

1.00 Initial

release

2014-07-24 JC

1.01

Add BIOS Checkpoints, Beep Codes; correct SD signal support; add SEMA CPU temperature
limitation

2014-09-24 JC

1.02

Correct specifications (CPU, memory, serial port, GPIO, eMMC, OS); add SW1 BIOS settings
description

2015-09-07 JC

1.03

Add clarification of single channel 24-bit EDID LVDS panel support by BOM option; correct B99
DDI0 signal name in 3.3 AB Signal Description

; update BIOS

2016-03-17 JC

Summary of Contents for Com Express nanoX-BT

Page 1: ...nanoX BT User s Manual Manual Revision 1 03 Revision Date March 17 2016 Part Number 50 1J053 1030...

Page 2: ...ignal support add SEMA CPU temperature limitation 2014 09 24 JC 1 02 Correct specifications CPU memory serial port GPIO eMMC OS add SW1 BIOS settings description 2015 09 07 JC 1 03 Add clarification o...

Page 3: ...n if advised of the possibility of such damages Environmental Responsibility ADLINK is committed to fulfill its social responsibility to global environmental preservation through compliance with the E...

Page 4: ...2 11 Environmental 11 2 12 Specification Compliance 11 2 13 Operating Systems 11 2 14 Functional Diagram 12 2 15 Mechanical Dimensions 13 3 Pinouts and Signal Descriptions 14 3 1 AB Pin Definitions 1...

Page 5: ...8 4 4 XDP Debug Header 29 4 5 nanoX BT Switch Settings 30 4 5 1 Switch Locations 30 4 5 2 SW1 BIOS Select and Mode Configuration Switch 30 5 Smart Embedded Management Agent SEMA 31 5 1 Board Specific...

Page 6: ...Super IO 50 7 3 9 ACPI and Power Management 50 7 3 10 Sound 51 7 3 11 Serial Port Console 51 7 3 12 Thermal 52 7 3 13 Miscellaneous 53 7 4 Boot 54 7 4 1 Boot Configuration 54 7 5 Security 55 7 5 1 Pa...

Page 7: ...7 9 1 Board to Board Connectors 66 9 2 Thermal Solution 67 9 2 1 Heat Spreaders 67 9 2 2 Heat Sinks 67 9 2 3 Installation 67 9 3 Mounting Methods 69 9 4 Standoff Types 70 Safety Instructions 71 Getti...

Page 8: ...CL 1 1 and support for H 264 MPEG2 VC1 VP8 hardware decode Graphics outputs include DDI ports supporting HDMI DVI DisplayPort and single channel 18 24 bit LVDS eDP is optional The nanoX BT is specific...

Page 9: ...and 24 kB 6 way L1 write back data cache 2MB L2 Cache E3845 N2930 and J1900 1MB L2 Cache E3827 E3826 E3825 and E3805 512k L2 Cache E3815 Memory Single channel non ECC 1333 1066 MHz soldered DDR3L mem...

Page 10: ...DID LVDS see 7 3 3 Graphics for supported resolutions Optional 24 bit EDID LVDS eDP Support by BOM option in place of LVDS DDI0 Supports DisplayPort HDMI DVI eDP 2 6 Audio Integrated Intel HD Audio in...

Page 11: ...age input Extreme Rugged Operating Temperature optional 40 C to 85 C standard voltage input Intel Atom E3800 Series processors only 2 11 Environmental Humidity 5 90 RH operating non condensing 5 95 RH...

Page 12: ...4 lanes 3 PCIe x1 Gen2 port 0 2 HD Audio 2x SATA 3Gb s port 0 1 1x USB 1 1 2 0 3 0 port 0 3x USB 1 1 2 0 port 1 3 1x USB 1 1 2 0 client port 7 XDP 60 pin PCIe x1 Gen2 port 3 eMMC 8GB 16GB 32GB LM73 t...

Page 13: ...nanoX BT Page 13 2 15 Mechanical Dimensions Top View Side View connector on bottom side Units mm...

Page 14: ...C_AD1 6 GBE0_MDI2 6 LPC_AD2 7 GBE0_MDI2 7 LPC_AD3 8 GBE0_LINK 8 LPC_DRQ0 9 GBE0_MDI1 9 LPC_DRQ1 10 GBE0_MDI1 10 LPC_CLK 11 GND FIXED 11 GND FIXED 12 GBE0_MDI0 12 PWRBTN 13 GBE0_MDI0 13 SMB_CK 14 GBE0_...

Page 15: ...4 GPI0 54 GPO1 55 RSVD 55 RSVD 56 RSVD 56 RSVD 57 GND 57 GPO2 58 PCIE_TX3 58 PCIE_RX3 59 PCIE_TX3 59 PCIE_RX3 60 GND FIXED 60 GND FIXED 61 PCIE_TX2 61 PCIE_RX2 62 PCIE_TX2 62 PCIE_RX2 63 GPI1 63 GPO3...

Page 16: ...I0_PAIR6 95 SPI_MOSI 95 DDI0_DDC_AUX_SEL 96 TPM_PP 96 USB_HOST_PRSNT 97 TYPE10 97 SPI_CS 98 SER0_TX 98 DDI0_CTRLCLK_AUX 99 SER0_RX 99 DDI0_CTRLDATA_AUX 100 GND FIXED 100 GND FIXED 101 SER1_TX CAN_TX 1...

Page 17: ...ut 5V signal level I O 3 3V Bi directional signal 3 3V tolerant I O 5V Bi directional signal 5V tolerant I O 3 3Vsb Input 3 3V tolerant active in standby state P Power Input Output REF Reference volta...

Page 18: ...nt LVDS_A0 eDP_TX2 LVDS_A0 eDP_TX2 LVDS_A1 eDP_TX1 LVDS_A1 eDP_TX1 LVDS_A2 eDP_TX0 LVDS_A2 eDP_TX0 LVDS_A3 LVDS_A3 A71 A72 A73 A74 A75 A76 A78 A79 LVDS Channel A differential pairs O LVDS LVDS_A_CK eD...

Page 19: ...t Ethernet Pin Description I O PU PD Comment GBE0_MDI0 GBE0_MDI0 GBE0_MDI1 GBE0_MDI1 GBE0_MDI2 GBE0_MDI2 GBE0_MDI3 GBE0_MDI3 A13 A11 A10 A9 A7 A6 A3 A2 Gigabit Ethernet Controller 0 Media Dependent In...

Page 20: ...tial pair I PCIE AC coupled off module PCIE_TX1 PCIE_TX1 A64 A65 PCI Express channel 1 Transmit Output differential pair O PCIE AC coupled on module PCIE_RX1 PCIE_RX1 B64 B65 PCI Express channel 1 Rec...

Page 21: ...O 3 3VSB Not supported USB7 USB7 B37 B37 USB differential data pairs for Port 7 I O 3 3VSB Client only USB_HOST_PRSNT B96 Module USB client may detect the presence of a USB host A high value indicate...

Page 22: ...ort 1 1 2 0 Port 2 1 2 0 Port 3 1 2 0 Port 7 Client P5 Port 0 3 0 USB_SSRX0 A22 USB_SSRX0 A23 USB_SSTX0 B22 USB_SSTX0 B23 ULPI 3 3 12 SPI BIOS only Signal Pin Description I O PU PD Comment SPI_CS B97...

Page 23: ...ve low input can be used to generate an SMI System Management Interrupt or to wake the system Power sourced through 5V standby rail and main power rails I 3 3VSB PU 10k 3 3VSB 3 3 15 I2C Bus Signal Pi...

Page 24: ...n power supply A high value indicates that the power is good This signal can be used to hold off Module startup to allow carrier based FPGAs or other configurable devices time to be programmed I 3 3V...

Page 25: ...0V nominal See section 7 Electrical Specifications for allowable input range If VCC5_SBY is used all available VCC_5V_SBY pins on the connector s shall be used Only used for standby and suspend funct...

Page 26: ...tors and pinouts LEDs and switches that are used on the module but are not included in the PICMG standard specification 4 1 Connector Switch and LED Locations Note The optional XDP Debug Header is loc...

Page 27: ...V provide from COM module 28 BMC Program interface continued OCD0B Include a jumper to connect OCD0A via 1K0 pull up to 3 3V_BMC 9 GND 29 PWRBTN 10 BIOS_DIS0 30 SYS_RESET 11 RST 31 CB_RESET 12 CLK33_L...

Page 28: ...T see 5 1 4 Exception Codes below LED2 Green Power Source 3Vcc S0 LED ON S3 S4 S5 LED OFF ECO mode LED OFF LED3 Red BMC output and same signal as WDT B27 on BtB connector Module power up LED OFF Watch...

Page 29: ...SoC 17 OBSDATA_A3 GPIO_S5 26 I O SoC 18 OBSDATA_C3 GPIO_S0_NC 19 I O SoC 19 GND GND NA 20 GND GND NA 21 OBSFN_B0 OPEN 22 OBSFN_D0 OPEN 23 OBSFN_B1 OPEN 24 OBSFN_D1 OPEN 25 GND GND NA 26 GND GND NA 27...

Page 30: ...the carrier In dual BIOS Failsafe mode both BIOS chips on the module are configured as SPI1 Only one of the two is connected to the SPI bus at any given time In case of BIOS failure of the primary SPI...

Page 31: ...r Type II Set Reset Disable Watchdog Timer Features auto reload at power up System Restart Cause Power loss BIOS Fail Watchdog Internal Reset External Reset Fail safe BIOS support In case of a boot fa...

Page 32: ...Main Current Function 5 1 2 Main Current The BMC of the nanoX BT implements a current monitor The current can be read by calling the SEMA function Get Main Current The function returns four 16 bit val...

Page 33: ...not needed or supported Exception Code Error Message 0 NOERROR 2 NO_SUSCLK 3 NO_SLP_S5 4 NO_SLP_S4 5 NO_SLP_S3 6 BIOS_FAIL 7 RESET_FAIL 8 POWER_FAIL 9 LOW_VIN 10 VCORE 11 VGFX 12 V1P05S 13 VMEM 14 V1...

Page 34: ...FF0000h FFFFFFFFh High Bios 0K 1MB 1MB DOS DRAM 6 2 I O Map Hex Range Device 20h 21h 24h 25h 28h 29h 2Ch 2Dh 30h 31h 34h 5h 38h 39h 3Ch 3Dh 8259 Master 40h 43h 50h 53h 8254s 61h 63h 65h 67h NMI Contro...

Page 35: ...IRQ PIRQ Note 1 10 Generic IRQ10 via SERIRQ PIRQ Note 1 11 Generic IRQ11 via SERIRQ PIRQ Note 1 12 Generic IRQ12 via SERIRQ PIRQ Note 1 13 Math Processor N A No 14 Primary IDE controller IRQ14 via SER...

Page 36: ...A PCIE Port 1 2 3 4 eMMC IGD Note 1 17 N A PCIE Port 1 2 3 4 Note 1 18 N A PCIE Port 1 2 3 4 SD Device HSUART Note 1 19 N A PCIE Port 1 2 3 4 AHCI controller Note 1 20 N A Gbe controller xHCI controll...

Page 37: ...Port 00h 1Ah 00h Internal Trusted Execution Engine 00h 1Bh 00h Internal HD Audio 00h 1Ch 00h Internal PCI Express Root port 1 00h 1Ch 01h Internal PCI Express Root port 2 00h 1Ch 02h Internal PCI Exp...

Page 38: ...18 Int1 INTB 17 Int2 INTC 18 Int3 INTD 19 INT Line SATA Controller xHCI Host Low Power Audio Engine TXE HD Audio EHCI Controller SMBus Controller Int0 INTE 20 INTF 21 INTF 21 INTG 22 INTH 23 Int1 INT...

Page 39: ...he function of each setting is described in the right hand column of the respective table Main Advanced Boot Security Save Exit System Information Processor Information VGA Firmware Version Memory Inf...

Page 40: ...Description CPU Brand String Info only Display CPU brand name Max CPU Speed Info only Display CPU frequency CPU Signature Info only Display CPU ID Number of Processors Info only Display number of pro...

Page 41: ...2 System Management Temperatures and Fan Speed Feature Options Description Temperatures and Fan Info only Board Temperatures Info only Current Read only Display current board temperature Startup Read...

Page 42: ...ead only The boot reason is the event which causes the reboot of the system 7 2 6 5 System Management Flags Feature Options Description Flags Info only BMC Flags Read only BIOS Select Read only Displa...

Page 43: ...Temperature 60 Specifies the temperature threshold at which the BMC turns on CPU fan the specified PWM level PWM Level 40 Select PWM level CPU Trigger Point 3 Read only Trigger Temperature 70 Specifi...

Page 44: ...fo L1 Code Cache Info only Display cache info L2 Cache Info only Display cache info L3 Cache Inf o only Display cache info Limit CPUID Maximum Disabled Enabled Disabled for Windows XP Execute Disabled...

Page 45: ...DVMT 5 0 Pre Allocated Fixed Graphics Memory size used by the Internal Graphics Device DVMT Total Gfx Mem 256MB Select DVMT5 0 Total Graphic Memory size used by the Internal Graphics Device LVDS Backl...

Page 46: ...isable SATA Controller Speed Gen1 Gen2 SATA speed support Gen1 or Gen2 SATA Port Configuration Submenu 7 3 4 1 SATA SATA Port Configuration Feature Options Description SATA Port Configuration Info onl...

Page 47: ...t is 100 ms for a Hub port the delay is taken from Hub descriptor Mass Storage Devices Info only List current USB mass storage devices 7 3 5 1 USB Chipset USB Configuration Feature Options Description...

Page 48: ...es PCI Express device No Snoop option Maximum Payload Auto 128 Bytes 256 Bytes 512 Bytes 1024 Bytes 2048 Bytes 4096 Bytes Set maximum payload of PCI Express device or allow system BIOS to select the v...

Page 49: ...n PCI Express Port x Enabled Disabled Enable or disable the PCI Express port x in the chipset ASPM Disabled L0s L1 L0sL1 Auto PCI Express Active State Power Management settings URR Disabled Enabled En...

Page 50: ...l Port Configuration Parallel Port Device Settings Change Settings Enabled Disabled IO 378h IRQ 5 Auto IO 378h IRQ 5 IO 378h IRQ 5 6 7 9 10 11 12 IO 278h IRQ 5 6 7 9 10 11 12 IO 3BCh IRQ 5 6 7 9 10 11...

Page 51: ...change data Both computers should have the same or compatible settings COM2 SIO Info only Console Redirection Disabled Enabled Console Redirection enable or disable Console Redirection Settings Submen...

Page 52: ...VT100 terminals Recorder Mode Disabled Enable With this mode enabled only text will be sent This is to capture terminal data Resolution 100x31 Disabled Enable Enables or disables extended terminal res...

Page 53: ...ubmenu Security Info only BIOS Security Configuration Submenu Trusted Computing Submenu 7 3 13 1 Miscellaneous SCC Configuration Feature Options Description SCC Configuration Info only SCC eMMC Suppor...

Page 54: ...indefinite waiting Bootup NumLock State On Off Select the keyboard NumLock state Quiet Boot Disabled Enabled Enable or disables Quiet Boot option Fast Boot Disabled Enabled Enables or disables boot w...

Page 55: ...nd legacy PXE OpROM Storage Do not launch UEFI only Legacy only Controls the execution of UEFI and legacy storage OpROM Video Do not launch UEFI only Legacy only Controls the execution of UEFI and leg...

Page 56: ...card Changes and Reset Yes No Reset system setup without saving any changes Save Options Info only Save Changes Yes No Save Changes done so far to any of the setup options Discard Changes Yes No Disca...

Page 57: ...l Platform Innovation Framework for EFI the Framework The Framework refers the following boot phases which may apply to various status code checkpoint descriptions Security SEC initial low level initi...

Page 58: ...rrors PEI 8 2 Standard Checkpoints 8 2 1 SEC Phase Status Code Description 0x00 Not used Progress Codes 0x01 Power on Reset type detection soft hard 0x02 AP initialization before microcode loading 0x0...

Page 59: ...ialization North Bridge module specific 0x19 Pre memory South Bridge initialization is started 0x1A Pre memory South Bridge initialization South Bridge module specific 0x1B Pre memory South Bridge ini...

Page 60: ...y initialization codes 0x4F DXE IPL is started PEI Error Codes 0x50 Memory initialization error Invalid memory type or incompatible memory speed 0x51 Memory initialization error SPD reading has failed...

Page 61: ...Recovery PPI is not available 0xF9 Recovery capsule is not found 0xFA Invalid recovery capsule 0xFB 0xFF Reserved for future AMI error codes 8 2 4 PEI Beep Codes of Beeps Description 1 Memory not Inst...

Page 62: ...zation is started 0x72 South Bridge devices initialization 0x73 South Bridge DXE Initialization South Bridge module specific 0x74 South Bridge DXE Initialization South Bridge module specific 0x75 Sout...

Page 63: ...ction below 0xAD Ready To Boot event 0xAE Legacy Boot event 0xAF Exit Boot Services event 0xB0 Runtime Set Virtual Address MAP Begin 0xB1 Runtime Set Virtual Address MAP End 0xB2 Legacy Option ROM Ini...

Page 64: ...evices are found 6 Flash update is failed 7 Reset protocol is not available 8 Platform PCI resource requirements cannot be met 8 2 7 ACPI ASL Checkpoint Status Code Description 0x01 System is entering...

Page 65: ...05 OEM SEC initialization before microcode loading 0x0A OEM SEC initialization after microcode loading 0x1D 0x2A OEM pre memory initialization codes 0x3F 0x4E OEM PEI post memory initialization codes...

Page 66: ...onnector with 0 5mm for a stacking height of 5 mm This connector can be used with 5 mm through hole standoffs SMT type Tyco 3 6318491 6 Foxconn QT002206 4141 3H 220 pin board to board connector with 0...

Page 67: ...ules 9 2 2 Heat Sinks A heat sink can be used as a thermal solution for a specific COM Express module and can have a fan or be fanless depending on the thermal requirements 9 2 3 Installation Install...

Page 68: ...Page 68 nanoX BT Step 3 Put heatsink on the COM Express module and assemble the heatsink onto the COM Express module Use the four M2 5 L 6mm screws provided to fasten the heatsink to the module...

Page 69: ...tion to the choice of 5 mm or 8mm board to board connectors there is the choice of Top and Bottom mounting In Top mounting the threaded standoffs are on the carrier board and the thermal solution is e...

Page 70: ...readed standoffs are DIP type and through hole standoffs are SMT type Other types not listed are available upon request 5mm through hole standoff SMT type P N 33 72000 0050 5mm threaded standoff DIP t...

Page 71: ...oid electrical shock and or damage to equipment Keep equipment away from water or liquid sources Keep equipment away from high heat or high humidity Keep equipment properly ventilated do not block or...

Page 72: ...86 21 5132 8988 Fax 86 21 5132 3588 Email market adlinktech com ADLINK Technology Beijing Address Rm 801 Power Creative E No 1 B D Shang Di East Rd Beijing 100085 China Tel 86 10 5885 8666 Fax 86 10...

Page 73: ...6 0585 Fax 82 31 786 0583 Email korea adlinktech com ADLINK Technology Singapore Pte Ltd Address 84 Genting Lane 07 02A Cityneon Design Centre Singapore 349584 Tel 65 6844 2261 Fax 65 6844 2263 Email...

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