cExpress-TL User’s Guide
PICMG COM.0 R3.0
Page 53
Copyright © 2021 ADLINK Technology, Inc.
4.4.6
PCIe Graphics Port (PEG)
Name
Pin #
Description
I/O
PU / PD
Comment
PEG_TX0-
D52
D53
PCI Express Graphics transmit differential pairs.
These are the same lines as PCIE_TX[16:31]+ and – in Module pin-
out Type 6
O PCIE
AC coupled on Module
PEG_RX0-
C52
C53
PCI Express Graphics receive differential pairs.
These are the same lines as PCIE_TX[16:31]+ and – in Module pin-
out Type 6
I PCIE
AC coupled off Module
PEG_TX1-
D55
D56
PCI Express Graphics transmit differential pairs.
These are the same lines as PCIE_TX[16:31]+ and – in Module pin-
out Type 6
O PCIE
AC coupled on Module
PEG_RX1-
C55
C56
PCI Express Graphics receive differential pairs.
These are the same lines as PCIE_TX[16:31]+ and – in Module pin-
out Type 6
I PCIE
AC coupled off Module
PEG_TX2-
D58
D59
PCI Express Graphics transmit differential pairs.
These are the same lines as PCIE_TX[16:31]+ and – in Module pin-
out Type 6
O PCIE
AC coupled on Module
PEG_RX2-
C58
C59
PCI Express Graphics receive differential pairs.
These are the same lines as PCIE_TX[16:31]+ and – in Module pin-
out Type 6
I PCIE
AC coupled off Module
PEG_TX3-
D61
D62
PCI Express Graphics transmit differential pairs.
These are the same lines as PCIE_TX[16:31]+ and – in Module pin-
out Type 6
O PCIE
AC coupled on Module
PEG_RX3-
C61
C62
PCI Express Graphics receive differential pairs.
These are the same lines as PCIE_TX[16:31]+ and – in Module pin-
out Type 6
I PCIE
AC coupled off Module
PEG_LANE_RV# D54 PCI Express Graphics lane reversal input strap. Pull low on the
Carrier Board to reverse lane order.
I 3.3V
Note
: Form the 16 lanes on the PEG port only lanes 0-3 are supported. The configuration is one x4
