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cExpress-AR User’s Guide

PICMG COM.0 R3.0

Page 44

Copyright © 2021 ADLINK Technology, Inc.

4.4.2.1.

PCH HSIO Lane Assignments (PCI Express)

Name

HSIO name on SOC

Comment

PCIE0 GPP

4

PCIE1 GPP

5

PCIE2 GPP

6

PCIE3 GPP

7

PCIE4 GPP

2

PCIE5 GPP

3

PCIE6 N/A

BOM option support by project basis through a PCIe switch

PCIE7 N/A

BOM option support by project basis through a PCIe switch

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Summary of Contents for cExpress-AR

Page 1: ...cExpress AR User s Guide PICMG COM 0 R3 0 Page 1 Copyright 2021 ADLINK Technology Inc cExpress AR Revision Rev 1 2 Date 2021 08 31 Part Number 50M 00014 1020 User s Guide...

Page 2: ...Page 2 Copyright 2021 ADLINK Technology Inc Revision History Revision Description Date Author 1 0 Initial release 2021 05 17 1 1 Update specifications AB CD Connector Signal Descriptions 2021 08 03 1...

Page 3: ...ctrical and Electronic Equipment WEEE directive Environmental protection is a top priority for ADLINK We have enforced measures to ensure that our products manufacturing processes components and raw m...

Page 4: ...s cables when installing mounting or un installing removing equipment To avoid electrical shock and or damage to equipment Keep equipment away from water or liquid sources Keep equipment away from hig...

Page 5: ...enoting special levels of information Note This information adds clarity or specifics to text and illustrations Caution This information indicates the possibility of minor physical injury component da...

Page 6: ...CA 95119 1208 USA Tel 1 408 360 0200 Toll Free 1 800 966 5200 USA only Fax 1 408 600 1189 Email info adlinktech com ADLINK Technology China Co Ltd 300 Fang Chun Rd Zhangjiang Hi Tech Park Pudong New A...

Page 7: ...Ethernet 13 2 6 Multi I O and Storage 14 2 7 Trusted Platform Module TPM 15 2 8 SEMA Board controller 15 2 9 Debug 15 2 10 Power 15 2 11 Mechanical and Environmental 16 3 Block Diagram 17 4 Pinout an...

Page 8: ...Port 45 4 4 4 DDI2 Port 48 4 4 5 DDI3 Port 51 4 4 6 PCIe Graphics Port PEG 54 4 4 7 Module Type Definition 56 4 4 8 Power and Ground 57 5 Additional Features 58 5 1 Debug Connector 59 5 2 Status LEDs...

Page 9: ...function diagram 17 Figure 2 Module rear side row and pin numbering 18 Figure 3 Module feature locations 58 Figure 4 cExpress AR and Debug Module 59 Figure 5 Module mechanical dimensions 67 Figure 6 H...

Page 10: ...ry error correction based on selected SKUs Combined with a configurable TDP to 10 watts while still support 8 core 6 core make fanless design achievable and well suited for mission critical or rugged...

Page 11: ...B L2 35 54W 8C 7CU AMD V2546 3 0 3 95GHz 3MB L2 35 54W 6C 6CU AMD V2718 1 7 4 15GHz 4MB L2 10 25W 8C 7CU AMD V2516 2 1 3 95GHz 3MB L2 10 25W 6C 7CU Memory Up to 64GB 3200 MT s DDR4 in two SODIMM socke...

Page 12: ...ndent on operating system Windows 10 64 bit Linux 64 bit 2 2 1 Display Interface Support LVDS Single dual channel 18 24 bit LVDS through eDP to LVDS IC supports DE mode and Hsync Vsync mode Max resolu...

Page 13: ...x8 Gen3 Lanes 16 23 configurable to 1 x8 or 2 x4 Other SMBus system I2C user LPC Note General Purpose Ports GPP 2 9 can support up to 6 devices SATA 0 1 count as one device refer to Functional Diagra...

Page 14: ...s are supported in standard BIOS including Super I O on the carrier COM Port Description IRQ Address Console Redirection Support COM 1 Supported by module SER0 A98 A99 via embedded controller 4 0x3F8...

Page 15: ...at cable connector for use with DB 30 x86 debug module Supports BIOS POST code LED embedded controller access SPI BIOS flashing internal power rail test points debug LEDs 2 10 Power Power Modes AT and...

Page 16: ...95 x 95 mm Operating Temperature Standard 0 C to 60 C Wide Voltage Input Storage 20 C to 80 C Humidity 5 90 RH operating non condensing 5 95 RH storage and operating with conformal coating Shock and V...

Page 17: ...ption eDP 4 lanes GPP 8 9 DDR4 SODIMM top side 3200 MT s non ECC ECC GPP 4 5 6 7 VGA eDP LVDS USB 2 0 Lane 0 7 SATA Port 0 1 SATA Port 2 3 PCIe Lane 0 3 PCIe Lane 4 5 2 5GbE GbE HDA SPI SMBus I2C GPIO...

Page 18: ...e below is a comprehensible list of all signal pins supported on the dual 220 pin COM Express connectors as defined for Type 6 in the PICMG COM 0 R3 0 specification Signals described in the specificat...

Page 19: ...R6 D15 DDI1_CTRLCLK_AUX A16 SATA0_TX B16 SATA1_TX C16 DDI1_PAIR6 D16 DDI1_CTRLDATA_AUX A17 SATA0_TX B17 SATA1_TX C17 RSVD D17 RSVD A18 SUS_S4 B18 SUS_STAT ESPI_RESET C18 RSVD D18 RSVD A19 SATA0_RX B19...

Page 20: ...LPC_SERIRQ ESPI_CS1 B50 CB_RESET C50 DDI3_PAIR3 D50 DDI2_PAIR3 A51 GND FIXED B51 GND FIXED C51 GND FIXED D51 GND FIXED A52 PCIE_TX5 B52 PCIE_RX5 C52 PEG_RX0 D52 PEG_TX0 A53 PCIE_TX5 B53 PCIE_RX5 C53 P...

Page 21: ...84 GND D84 GND A85 GPI3 B85 VCC_5V_SBY C85 PEG_RX10 D85 PEG_TX10 A86 RSVD B86 VCC_5V_SBY C86 PEG_RX10 D86 PEG_TX10 A87 eDP_HPD B87 VCC_5V_SBY C87 GND D87 GND A88 PCIE0_CK_REF B88 BIOS_DIS1 C88 PEG_RX1...

Page 22: ...8 VCC_12V A109 VCC_12V B109 VCC_12V C109 VCC_12V D109 VCC_12V A110 GND FIXED B110 GND FIXED C110 GND FIXED D110 GND FIXED Notes STRIKETHROUGH entries are not supported functions on this product PCIe l...

Page 23: ...3V tolerant I O 5V Bi directional signal 5V tolerant I O 3 3VSB Input or output 3 3V tolerant active in standby state DDC Display Data Channel PCIE PCI Express compatible differential signal PEG PCI...

Page 24: ...AC_RST HDA_RST A30 Reset output to CODEC active low O 3 3VSB AC_SYNC HDA_SYNC A29 Sample synchronization signal to the CODEC s O 3 3V AC_BITCLK HDA_BITCLK A32 Serial data clock generated by the exter...

Page 25: ...150R Shall also be terminated on the carrier with 150 resistor to ground close to VGA connector VGA_BLU B92 Blue for monitor Analog DAC output designed to drive a 37 5 Ohm equivalent load O Analog PD...

Page 26: ...elow Pin LVDS mode eDP mode A71 A72 LVDS_A0 LVDS_A0 eDP_TX2 eDP_TX2 A73 A74 LVDS_A1 LVDS_A1 eDP_TX1 eDP_TX1 A75 A76 LVDS_A2 LVDS_A2 eDP_TX0 eDP_TX0 A78 A79 LVDS_A3 LVDS_A3 A81 A82 LVDS_A_CK LVDS_A_CK...

Page 27: ..._B0 LVDS_B0 LVDS_B1 LVDS_B1 LVDS_B2 LVDS_B2 LVDS_B3 LVDS_B3 B71 B72 B73 B74 B75 B76 B77 B78 LVDS Channel B differential pairs O LVDS LVDS_B_CK LVDS_B_CK B81 B82 LVDS Channel B differential clock O LVD...

Page 28: ...ifferential pairs O PCIE AC coupled off module eDP_VDD_EN A77 eDP power enable O 3 3V PD 100K eDP_BKLT_EN B79 eDP backlight enable O 3 3V PD 100K eDP_BKLT_CTRL B83 eDP backlight brightness control O 3...

Page 29: ...NK A8 Gigabit Ethernet Controller 0 link indicator active low OD 3 3VSB LED behaviour is TBC GBE0_LINK100 A4 Gigabit Ethernet Controller 0 100Mbit sec link indicator active low OD 3 3VSB LED behaviour...

Page 30: ...ed on Module SATA2_TX SATA2_TX A22 A23 Serial ATA channel 2 Transmit Output differential pair O SATA Not supported SATA2_RX SATA2_RX A25 A26 Serial ATA channel 2 Receive Input differential pair I SATA...

Page 31: ...ress channel 2 Receive Input differential pair I PCIE AC coupled off Module PCIE_TX3 PCIE_TX3 A58 A59 PCI Express channel 3 Transmit Output differential pair O PCIE AC coupled on Module PCIE_RX3 PCIE_...

Page 32: ...IE0 GPP 4 PCIE1 GPP 5 PCIE2 GPP 6 PCIE3 GPP 7 PCIE4 GPP 2 PCIE5 GPP 3 PCIE6 N A BOM option support by project basis through a PCIe switch PCIE7 N A BOM option support by project basis through a PCIe s...

Page 33: ...d and data bus I O 3 3V Chipset has internal PU 50K 30 LPC_FRAME B3 LPC frame indicates the start of an LPC cycle O 3 3V Chipset has internal termination 50K 30 LPC_DRQ0 LPC_DRQ1 B8 B9 LPC serial DMA...

Page 34: ...mpliant USB6 USB6 A37 A36 USB differential data pairs for Port 5 I O 3 3VSB USB 1 1 2 0 compliant USB7 USB7 B37 B37 USB differential data pairs for Port 6 I O 3 3VSB USB 1 1 2 0 compliant USB_0_1_OC B...

Page 35: ...rent sense USB ports 6 and 7 A pull up for this line shall be present on the module An open drain driver from a USB current monitor on the carrier board may drive this line low I 3 3VSB PU 10K 3 3VSB...

Page 36: ...ck from module to carrier board SPI BIOS flash O 3 3VSB SPI_POWER A91 Power supply for Carrier Board SPI sourced from Module nominally 3 3V The Module shall provide a minimum of 100mA on SPI_POWER Car...

Page 37: ...er temp situation I 3 3VSB THRMTRIP A35 Active low output indicating that the CPU has entered thermal shutdown O 3 3V PU 1K 3 3V FAN_PWMOUT B101 Fan speed control Uses the Pulse Width Modulation PWM t...

Page 38: ...ystem Management Bus Alert active low input can be used to generate an SMI System Management Interrupt or to wake the system Power sourced through 3 3V standby rail and main power rails I 3 3VSB Note...

Page 39: ...GPI 1 A63 General purpose input pins Pulled high internally on the module I 3 3V PU 10K 3 3V GPI 2 A67 General purpose input pins Pulled high internally on the module I 3 3V PU 10K 3 3V GPI 3 A85 Gene...

Page 40: ...nt suspend operation used to notify LPC devices O 3 3VSB SUS_S3 A15 Indicates system is in Suspend to RAM state Active low output An inverted copy of SUS_S3 on the carrier board also known as PS_ON ma...

Page 41: ...used P 8 5 20 V VCC_5V_SBY B84 B85 B86 B87 Standby power input 5 0V nominal If VCC5_SBY is used all available VCC_5V_SBY pins on the connector s shall be used Only used for standby and suspend functi...

Page 42: ...USB data path on USB1 I PCIE AC coupled on module USB_SSTX1 USB_SSTX1 D6 D7 Additional Transmit signal differential pairs for the SuperSpeed USB data path on USB1 O PCIE AC coupled on module USB_SSRX2...

Page 43: ...D19 D20 PCI Express channel 6 Transmit Output differential pair O PCIE AC coupled on Module By a PCIe switch project basis PCIE_RX6 PCIE_RX6 C19 C20 PCI Express channel 6 Receive Input differential p...

Page 44: ...c 4 4 2 1 PCH HSIO Lane Assignments PCI Express Name HSIO name on SOC Comment PCIE0 GPP 4 PCIE1 GPP 5 PCIE2 GPP 6 PCIE3 GPP 7 PCIE4 GPP 2 PCIE5 GPP 3 PCIE6 N A BOM option support by project basis thro...

Page 45: ...PAIR5 DDI1_PAIR5 C29 C30 DDI1_PAIR6 DDI1_PAIR6 C15 C16 DDI1_HPD C24 DP1_HPD HDMI1_HPD DDI1_CTRLCLK_AUX D15 DP1_AUX HMDI1_CTRLCLK DDI1_CTRLCLK_AUX D16 DP1_AUX HMDI1_CTRLDATA DDI1_DDC_AUX_SEL D34 DDI1_D...

Page 46: ...nplug and notification of the link layer I 3 3V PD 100K Module must tolerate high level in stand by mode The carrier board shall include a blocking FET on DP1_HPD to prevent back drive current from da...

Page 47: ...100 nF DC blocking capacitors shall be placed on the Carrier TMDS1_CLK TMDS1_CLK D36 D37 HDMI Port Differential Pair Clock Lines HDMI_HPD C24 Detection of Hot Plug Unplug and notification of the link...

Page 48: ...TMDS2_CLK DDI2_HPD D44 DP2_HPD HDMI2_HPD DDI2_CTRLCLK_AUX C32 DP2_AUX HMDI2_CTRLCLK DDI2_CTRLCLK_AUX C33 DP2_AUX HMDI2_CTRLDATA DDI2_DDC_AUX_SEL C34 DDI2_DDC_AUX_SEL DDI2_DDC_AUX_SEL Note Dual Mode HD...

Page 49: ...nplug and notification of the link layer I 3 3V PD 100K Module must tolerate high level in stand by mode The carrier board shall include a blocking FET on DP1_HPD to prevent back drive current from da...

Page 50: ...100 nF DC blocking capacitors shall be placed on the Carrier TMDS2_CLK TMDS2_CLK D49 D50 HDMI Port Differential Pair Clock Lines HDM2_HPD D44 Detection of Hot Plug Unplug and notification of the link...

Page 51: ...TMDS3_CLK DDI3_HPD C44 DP3_HPD HDMI3_HPD DDI3_CTRLCLK_AUX C36 DP3_AUX HMDI3_CTRLCLK DDI3_CTRLCLK_AUX C37 DP3_AUX HMDI3_CTRLDATA DDI3_DDC_AUX_SEL C38 DDI3_DDC_AUX_SEL DDI3_DDC_AUX_SEL Note Dual Mode HD...

Page 52: ...nplug and notification of the link layer I 3 3V PD 100K Module must tolerate high level in stand by mode The carrier board shall include a blocking FET on DP1_HPD to prevent back drive current from da...

Page 53: ...100 nF DC blocking capacitors shall be placed on the Carrier TMDS3_CLK TMDS3_CLK C49 C50 HDMI Port Differential Pair Clock Lines HDM3_HPD C44 Detection of Hot Plug Unplug and notification of the link...

Page 54: ...odule PEG_TX2 PEG_TX2 D58 D59 PCI Express Graphics transmit differential pairs These are the same lines as PCIE_TX 16 31 and in Module pin out Type 6 O PCIE AC coupled on Module PEG_RX2 PEG_RX2 C58 C5...

Page 55: ...Type 6 O PCIE AC coupled on Module PEG_RX6 PEG_RX6 C71 C72 PCI Express Graphics receive differential pairs These are the same lines as PCIE_TX 16 31 and in Module pin out Type 6 I PCIE AC coupled off...

Page 56: ...sent X TYPE2 TYPE1 TYPE0 X X X Pinout Type 1 X X X Pinout Type 10 NC NC NC Pinout Type 2 NC NC GND Pinout Type 3 NC GND NC Pinout Type 4 NC GND GND Pinout Type 5 GND NC NC Pinout Type 6 GND NC GND Pin...

Page 57: ...D105 D106 D107 D108 D109 Primary power input supports wide range 5 20V input All available VCC_12V pins on the connector s shall be used P 8 5 20 V GND C1 C2 C5 C8 C11 C14 C21 C31 C41 C51 C60 C70 C73...

Page 58: ...witches and additional items located on the module and not necessarily included in the PICMG standard spec ification The locations of these items is as below Figure 3 Module feature locations BIOS def...

Page 59: ...particular useful during carrier design and bring up phase It offers access to the following critical parts of the module z Test points measurement of internal power rails z I2C bus for BIOS POST cod...

Page 60: ...odes Table below LED2 Green Power Source 3Vcc S0 LED ON S3 S4 S5 LED OFF ECO mode LED OFF LED3 Red BMC output and same signal as WDT B27 on BtB connector Module power up WD LED LED OFF Watchdog counti...

Page 61: ...ROR 2 NO_SUSCLK 3 NO_SLP_S5 4 NO_SLP_S4 5 NO_SLP_S3 6 BIOS_FAIL 7 RESET_FAIL 8 RESETIN_FAIL 9 NO_CB_PWROK 10 CRITICAL_TEMP 11 POWER_FAIL 12 VOLTAGE_FAIL 13 RFID_MEMFAIL No Used 14 NO_VDDQ_PG 15 NO_V1P...

Page 62: ...Express AR User s Guide PICMG COM 0 R3 0 Page 62 Copyright 2021 ADLINK Technology Inc 5 4 Fan Connector Connector type JVE 24W1125A 04M00 Name Description 1 FAN_PWMOUT 2 FAN_TACHIN 3 GND 4 12V 4 3 2 1...

Page 63: ...t of BIOS default settings perform the following steps 1 Shut down the system 2 Keep the BIOS Setup Defaults Reset Button pressed and boot up the system You can release the button when the BIOS prompt...

Page 64: ...in the SPI0 slot on the carrier In dual BIOS Failsafe mode both BIOS chips on the module are configured as SPI1 Only one of the two is connected to the SPI bus at any given time In case of failure of...

Page 65: ...he task the system is currently executing Checkpoints are very useful in aiding software developers or technicians in debugging problems that occur during the pre boot process on production hardware A...

Page 66: ...cExpress AR User s Guide PICMG COM 0 R3 0 Page 66 Copyright 2021 ADLINK Technology Inc 7 Software Support 7 1 Operating Systems Windows 10 IOT Enterprise 64 bit Windows 10 64 bit Ubuntu 20 04 planning...

Page 67: ...eters Tolerances should be 0 25mm unless otherwise noted The tolerances on the module connector locating peg holes dimensions 16 50 6 00 16 50 18 00 should be 0 10mm 0 0 4 16 5 74 2 80 95 4 91 4 91 4...

Page 68: ...cExpress AR User s Guide PICMG COM 0 R3 0 Page 68 Copyright 2021 ADLINK Technology Inc 8 2 Thermal Solutions 8 2 1 Heatspreader HTS Figure 6 Heatspreader HTS Dimensions mm...

Page 69: ...cExpress AR User s Guide PICMG COM 0 R3 0 Page 69 Copyright 2021 ADLINK Technology Inc 8 2 2 Heatsink THS Figure 7 Heatsink THS Dimensions mm...

Page 70: ...cExpress AR User s Guide PICMG COM 0 R3 0 Page 70 Copyright 2021 ADLINK Technology Inc 8 2 3 Heatsink High Profile THSH Figure 8 Heatsink High Profile THSH Dimensions mm...

Page 71: ...cExpress AR User s Guide PICMG COM 0 R3 0 Page 71 Copyright 2021 ADLINK Technology Inc 8 2 4 Heatsink with Fan THSF Figure 9 Heatsink with Fan THSF Dimensions mm...

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