AmITX-BE-G
Page 55
Feature
Options
Description
HW initialized data will be used.
Clock Power Management
Disabled
Enabled
If supported by hardware and set to 'Enabled', the device is
permitted to use CLKREQ# signal for power management of
Link clock in accordance to protocol defined in appropriate form
factor specification.
Compliance SOS
Disabled
Enabled
If supported by hardware and set to 'Enabled', this will force
LTSSM to send SKP Ordered Sets between sequences when
sending Compliance Pattern or Modified Compliance Pattern.
Hardware Autonomous Width
Disabled
Enabled
If supported by hardware and set to 'Disabled', this will disable
the hardware's ability to change link width except width size
reduction for the purpose of correcting unstable link operation.
Hardware Autonomous Speed
Disabled
Enabled
If supported by hardware and set to 'Disabled', this will disable
the hardware's ability to change link speed except speed rate
reduction for the purpose of correcting unstable link operation.
8.3.7.3.
PCI and PCIe > SB GPP Port Configuration
Feature
Options
Description
SB GPP Function
Disabled
Enabled
GPP Port Link Configuration
x4 mode
2:2 mode
2:1:1 mode
1:1:1:1 mode
GPP Link ASPM
Disabled
L0s
L1
L0s+
L1
GPP Gen2
Disabled
Enabled
UMI Gen2
Disabled
Enabled
GPP HW Compliance Mode
Disabled
Port A
Port B
Port C
Port D
SB GPP LANE REVERSAL
Disabled
Enabled
UMI PHY PLL Power Down Disabled
Enabled
SB GPP PHY PLL Power Down
Disabled
Enabled
