Hardware Registers
27
4.3
Analog Output Status Register
PCI-6208/6216-GL Series cards use series bus architecture to
communicate with digital-to-analog converters, hence there is
a delay for digital values to be output. The data transfer rate for
every DA data write is 2.2 µs, therefore the software driver
must wait 2.2 µs before sending any other data to any analog
output port. While the DA value is being sent, the Data_Send
bit is set to 'H'. The software driver should check this bit before
writing any data to the output port. Writing any value to the ana-
log output control register prior to this status bit is being "L" is
not allowed. This register is read only.
Table 4-2: Analog Output Status Register
4.4
Digital Output Register
Signals D0 through D3 are digital output signals written to each
output channel. Signals D4 to D7 are reserved.
Table 4-3: Digital Output Register
Offset Address
D15~D1
D0
0x00 X
Data_Send
Offset Address
D7
D6
D5
D4
D3
D2
D1
D0
0x40 X
X
X
X
DO3
DO2
DO1
DO0
