ADC Super Net S-100 Technical Manual Download Page 3

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Summary of Contents for Super Net S-100

Page 1: ...nCHNICAL MANDAt for SUPER NET S 100 Single Board Computer 7201 Garden Grove Blvd Suite E Garden Grove CA 92641...

Page 2: ...to 4 external floppy disk drives and an external Centronlcs parallel interface prlnter all on one board The SUPER NET sac contains 1 Z 89A cpu 2 Floppy disk c ntroller up to 4 drives a or 5 1 4 3 64...

Page 3: ...Pla parallel port channel A 11 4 4 Pla parallel port channel B 11 4 5 Control timer Interrupt circuit 11 4 6 Floppy Disk controller Il 4 7 Floppy disk control port 12 4 8 Extended address port 13 4 9...

Page 4: ...2 10 3 la 4 1a 5 10 6 10 1 10 8 10 9 1a 9 1 Installed Jumpers 8 inch drive configuration 5 25 inch drive configuration Shugart 800 drive shugart 850 MP1 dr ive MFE model 700 MITsUB1sat model M2894 NEC...

Page 5: ...K 32K 48K 48K 64K under software control This a1low t CPU to access bank switchab1e external memory on the 5100 bus The memory has an access time of 200ns Refresh is done during 280 Ml cycles and duri...

Page 6: ...tions plus a variety of interrupt modes Modem control s1 nals are available at each seria1 connector There are two switch selectible baud rate generators for baud rates of 50 to 19 2 k baud Note The s...

Page 7: ...er for synchronous baud rates or 10n9 c ock times 1 7 5100 Bus Interface The 5100 bus interface provides the signa1s necessary for an 8 bit bus master as described by the IEEE 696 bus specification Ve...

Page 8: ...d 2 1 Eprom Enable Disab1e Switching EPROM on F033 3E4F MVI A 01001111B RESET POWER ON JUMP AND ENABLE MEMORY EPROM ON F035 0316 OUT 168 WRITE Ta CONTROL PORT Switching EPROM off F033 3E4F MVI A 01101...

Page 9: ...SC will terminate any command The coldboot loader will select and home drive 0 Track 0 sector 1 will be read into memory at location 0 Single density is assumed for track 0 If an errOL occures an erro...

Page 10: ...F4D9 3E8C MVI A a8ea GET READ COMMAND F4DB 030C OUT FOC ISSUE COMMAND F4DD 00 NOP FDCRD F4DE D814 IN WAIT WAIT FOR INTRQ F4E0 87 ORA A OR ORQ F4El F2EBF4 JP BOOTON EXIT IF INTRQ F4E4 DB0F IN FDCDATA G...

Page 11: ...us Control Port PlO Channel A Data port PlO Channel A Control Port PlO Channel B Data port PlO Channel B Control Port CTC Channel 0 Control port CTC Channel 1 Control portol CTC Channel 2 Control port...

Page 12: ...Parallel Interface Port B See Appendix B This port can be jumpered via jumpers E through P ta the 5100 Vectored Interrupt lines or to connector J2 see sec 6 0 06 07 ReaJ W r i te Write PlO Channel B D...

Page 13: ...y disk controller INTRQ status bit is placed on the data bus as bit 07 This bit can be tested to determine if data is to be transfered of if the command is complete 1 07 1 06 1 05 1 04 1 03 1 02 Dl DO...

Page 14: ...bit 00 1 1 1 1 1 1 Disk drive select bit Dl 1 1 1 1 Oon t care 1 1 1 1 Oensity 0 single l double 1 1 1 Don t care 1 1 Don t care 1 Don t care Don t care 4 8 Extended address port 15 Write port Write S...

Page 15: ...rticular bank is switched off external 5100 memory can be accessed in that banks address range This feature allows external memory to be added to the system for multi user operating systems Bit D5 of...

Page 16: ...n J2 33 M Select S100 interrupt vector VIS or Parallel Port B bit 05 on J2 35 N Select S100 interrupt vector VI6 or Parallel Port B bit 06 on J2 37 P Select 100 interrupt vector VI7 or Parallel Port B...

Page 17: ...nous applications Jumper C is located near J5 00 1 l 1 Connector JS pin 9 1 2 1 SIO TxiRX clock input 1 3 1 Baud rate generator channel B Install Plug between posts l 2 for external SIO clock Install...

Page 18: ...ris 10ct ted nea r connec to r J 2 1 2 3 Insta11 P1ug between posts 1 2 to connect the PlO bit 00 to J2 pin 25 when the PlO bit is programmed for input output Install Plug between posts 2 3 to connec...

Page 19: ...1 3 between posts 1 2 to connect the PlO bit 03 to J2 pin 25 when the PlO bit is programmed for input output Install Plug between posts 2 3 to connect the PlO bit Dl to the vectored interrupt line VI...

Page 20: ...ts 1 2 to connect the PlO bit 06 to J2 pin 25 when the PlO bit is pr grammed for input output Install Plug between posts 3 to connect the PlO bit 06 to the vectored interrupt line VI6 when the PlO bi...

Page 21: ...2K long it appears twice F800H FC00H and FBFFH FFFFH 6 15 s Define floppy disk connector for eight five inch drives and FDC chip type This jumper is located U26 of 1 1 2 1 3 1 4 1 15 6 1 7 8 _ _ Insta...

Page 22: ...ole switch located near U54 It is split into two sections Switches 1 2 3 4 set the baud rate for the SIO channel B and switches 5 6 7 8 set the baud rate for the 510 channel A SW1 8 7 5 4 1 312 1 1 Ch...

Page 23: ...T ground 11 PA3 PlO Channel A data bit 03 12 PA3 RET ground 13 PA4 PlO Channel A data bit 04 14 PA4 RET ground 15 PAS PlO Channel A data bit 05 16 PA5 RET ground 17 PA6 PlO Channel A data bit 06 18 PA...

Page 24: ...26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 ground A1ternate Head 2 ground NiC ground NiC ground Nic ground Nic ground Nic g...

Page 25: ...RxCA 10 GND 11 NiC 12 16 VOLTS 13 16 VOLTS 14 S VOLTS gro und Write protect ground Read data ground Motor on ground Nic Serial port Channel A Data Carrer Detect Channel A Sync Detect Receive data Cle...

Page 26: ...arall l 1 1 1 Floppy diskl 1 A Serial B 1 1 ports 1 1 1 controllerl 1 ports 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 clock 1 1eproml 1 CPU 1 1 Ram Array 1 1 11 1 12k 4k 1 1 1 1 1 1 1 1 1 1 1 1 1 1 da...

Page 27: ...0 A internal TX Rx clock for 510 B internal Eight inch Drive selection Select vector line VI0 Parallel Port B bit 00 on J2 25 Parallel Port B bit Dl on J2 27 parallel Port B bit 02 on J2 29 Parallel P...

Page 28: ...internal Eight inch Drive selection Select vector line VI0 Parallel Port B bit 00 on J2 25 Parallel Port 8 bit Dl on J2 27 parallel Port B bit D2 on J2 29 Paralle1 Port B bit D3 on J2 31 Paralle1 Por...

Page 29: ...800 Jumpers Disk drive jumpers Remove al jumpers on the disk drive Install jumpers as follows Jumper y Jumper 0 Jumper T3 T4 T5 T6 c Jumper Tl Jumper 800 Jumper X Jumper A Jumper B J umper OS j umper...

Page 30: ...10 4 Shugart 850 DisK drive Jumpers Jumper 28 Jumper D Jumper A Jump r B Jumper R Jumper 1 Jumper Z Jumper 850 Jumper S2 Jumper IW Jumper FS Jumper RS Jumper OS 29...

Page 31: ...10 8 EC lOo el FDl160 Oizk driv Jumpe 3 Install jumpers as follows Jumper C Jumper N Jumper HLS Jump er _M Jumper PRt Jumper DLD Jumper FU 33...

Page 32: ...10 9 QUME data track 8 Disk drive jumpers Install jumpers as follows OS1 OR OS2 o C OPTIONAL OC 2S 34...

Page 33: ...LD __ 1 l Ot0 11 1 14 f 141 IJSI L 245 fJl 1 2 f L I91 1 2 9 1 4 d 1 1 f il I 14 11 I f lJ l J Dl 04 01 i A 6_ i Aq 7 Ait 1 11 il AB Al 4 AI I Rt 3 1 5 1 _ 4 L 12 l i01 _ UI8 1 00 DI n no 04 O 14 L Dl...

Page 34: ...1 1 llHI SoH I j j Uob U 8 4 L H40 J DI 1 Ci UH 9 11 _ 1 8 JL 3Z 1 D J J IILlo _ 6 1 1 1 1 1 eA0 1 ent 11 PlA 6A3 BA4 eA n Mb A BAli BAt t eA o liAI 4 l AII AA11 BAn BAU BA VE 7 1 Joa eA0 CAI 11 50 Cq...

Page 35: ...No 34 2 7 1 1 3 5 li 7 I Il 0 I 1 15 11 l f l lll Il n 2 a 10 12 f4 ob IO 20 n t Z4 t 7 za t o t 1 U9 5WI 9 fi I 16 14 le 1 00 r QL _ 02 1 DJ oc 04 0 III Ob 07 1 J _ _ _ _ __ 5 t 4 3 L 2 L l_ mrf s _...

Page 36: ...WH 1 II e 1 140b 12 8 la K a ve nO H I Il Q a Il 0 l f 1 J J I L n L l FDce t Ijt ll 4 l f i ClI 1 2_2 tu l r or IS l r Bl Hll Q 0 12 0 e J Q Je 1 IR 0 OR Ne LSID 0 1 5 0 Cl RI 1 220 1 V lO K U3 if 10...

Page 37: ...S _ L 7 L l l _ 1 __ 4 _ J _ _ SNG tl If _ _ e POlA CoNIl b8 tSS 12 P2 e XO lL _ 1J L ru C m L 5 8 m L _ f CC D5R 1 IO S R 1C 60 i R 8 L_ r 20 rqx BA hO 2 1 6 PS NEI...

Page 38: ...IJ t B 03 IS ra 0 L aoS 7 1 aD c l J 7 8 J P p n S L l4 27 L PB 1 L f5 1 z e 1 2 P oP 31 Pl 3 a S Jr 1 2 33 __ PB i Au t J 61 1 3 3 7 B c 4 V t 6 3 1 p 7 pl t 1 Y1 Z Jf S 1 OA D6 z TIO 3 1 1 l S 1 2 0...

Page 39: ...ay out of SUPER NET with jUI C peI areas Be sure ta notice that Pin 1 of the header connector on the top of the board is on the left do no t plug disk and llO cable in hackward r1AY CAUSE DN1AGES Than...

Page 40: ...1 r J f iolJ c...

Page 41: ...Po r fa11 bt 8 signal Temp rary master pclorlty bit 3 Extended address bit 18 Extended address bit 16 Extended address bit 17 The control signal to disable the 8 status signals The control signal to...

Page 42: ...rupt acknowledqe instruction fetch cycle s The status signal whlch acknowledges that a HLT instruction MS been executed 2 Hz c1ock Not required to be synchronous witll any o ther bus signal Common wi...

Page 43: ...ntifying the presence of val id data on DO b or data bus The control signal that requests data on the DI bus or data bus fran the currently addressed slave Address bit 0 least significant Address bit...

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