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12. Watchdog Timer
The watchdog timer feature of the NPC-486E provides a means to insure the integrity of
system operation. When enabled, the timer must be refreshed by the system software
every 250 milliseconds or it will assert a hardware signal which will reset the system.
12.1 Enable
The timer circuit function is enabled by a jumper strap, E14, and by a control bit in a
software accessible register.
Watchdog timer circuit disabled
E14
Watchdog timer circuit enabled
Software control of the watchdog circuit is accomplished by manipulating the contents of
the NPC-486E’s Custom I/O register 1. This register controls many special features of the
NPC-486E, the watchdog timer among them. See Appendix C for a description of this
register. Bit 2 of register 1 is the software timer enable. A “1” in this location enables the
timer for operation (if E14 is IN as well). A “0” at this location disables the timer circuit.
The default value for this bit is “0”.
12.2
Operation
When enabled, the timer circuit must be continually strobed to prevent it from entering the
alarm condition. Strobing is done by reading the NPC-486E’s Custom I/O Index register.
Should a time-out occur, the circuit will trigger a reset.
The timer circuit is based on the Maxim MAX1232 (also available from Dallas as part
DS1232). The circuit has been designed for 600ms as the time-out period. The
specification for the 1232 defines this as a typical value. The actual time-out can range
from 250ms to 1000ms. Strobe software must assume the minimum time-out of 250ms,
and shut-down circuitry should assume the maximum, 1000ms.
