AT-1212 User Guide and Specifications - 17 -
www.activetechnologies.it
LabView Interface
Host Side
Host VI - CLIP
Description
InitModule1212(Host).vi
Initialize the 1212 adapter module. If the adapter has been
correctly initialized, DAC A Aligned / DAC B Aligned and FPGA
DCM Locked indicators must be true.
To enter in Debug mode, set DEBUG as true.
Input Parameters
FPGA VI Reference IN
: FPGA reference
RIO Device
CLOCK SELECTION
:DAC Clock source selection
INTERNAL CLOCK
:Clock Generator input source
Error in
Output Parameters
FPGA DCM LOCKED
: if true, the FPGA DCM has locked
DAC A Aligned
: if true the first DAC has been correctly initialized
and aligned
DAC B Aligned
: if true the second DAC has been correctly
initialized and aligned
Error out
IMPORTANT NOTE
: the user
should NOT
hit the
ABORT
button
during the initialization
SetVocm.vi
Set the Vocm voltage
Summary of Contents for AT-1212
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