AT-1212 User Guide and Specifications - 11 -
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FPGA I/O Interface
datadac_in0_ch0,datadac_in2_ch0,
datadac_in4_ch0, datadac_in6_ch0
Input[13..0]
Data for DAC Port 1 CH0
The user needs to send data to the Clip Inputs
at IO Module Clock rate (156.25 MHz); the
datadac_in0..datadac_in6 are internally
serialized by 4 to obtain a data rate of 625
MS/s.
datadac_in1_ch0,datadac_in3_ch0,
datadac_in5_ch0, datadac_in7_ch0
Input[13..0]
Data for DAC Port 2 CH0
The user needs to send data to the Clip Inputs
at IO Module Clock rate (156.25 MHz); the
datadac_in1..datadac_in7 are internally
serialized by 4 to obtain a data rate of 625
MS/s.
datadac_in0_ch1,datadac_in2_ch1,
datadac_in4_ch1, datadac_in6_ch1
Input[13..0]
Data for DAC Port 1 CH1
The user needs to send data to the Clip Inputs
at IO Module Clock rate (156.25 MHz); the
datadac_in0..datadac_in6 are internally
serialized by 4 to obtain a data rate of 625
MS/s.
datadac_in1_ch1,datadac_in3_ch1,
datadac_in5_ch1, datadac_in7_ch1
Input[13..0]
Data for DAC Port 2 CH1
The user needs to send data to the Clip Inputs
at IO Module Clock rate (156.25 MHz); the
datadac_in1..datadac_in7 are internally
serialized by 4 to obtain a data rate of 625
MS/s.
datai2c0..datai2c5
Input[7..0]
Data transferred by I2C write
readdataI2C
Output[7..0] Data retrieved by I2C read
startRDI2C
Input
Start I2C bus read
startWRI2C
Input
Start I2C bus write
reset_in
Input
Reset the DCMs and FAM
lockedfast
Output
Check if the FPGA DCM has locked or not
Summary of Contents for AT-1212
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