Actel ProASIC3/E, User Manual, Page: 33 / 106

Design Implementation
ProASIC3/E Starter Kit User’s Guide and Tutorial 33
Design Implementation
During design implementation, Actel Designer places-and-routes the design.
Place-and-Route
Start Designer from Libero IDE to place-and-route the design.
Timing Simulation
Perform timing simulation on the design after place-and-route in Designer. Timing simulation requires information
extracted and back-annotated from Designer.
Optional Tools
The tools listed in Table 6-1 provide optional functions that are not required in a basic design. Use these tools to
perform static timing analysis, power analysis, customize I/O placements and attributes, and view the netlist. After
place-and-route, perform the post-layout (timing) simulation.
For more information on the tools described in the above section, refer to the Designer User’s Guide.
Programming
Program the device with programming software and hardware from Actel or a supported third party programming
system. Refer to the Designer User’s Guide, Silicon Sculptor User’s Guide, and FlashPro User’s Guide for information
about programming an Actel device. These guides can be found at
http://www.actel.com/techdocs/manuals/
default.aspx .
System Verification
Use the Logic Navigator tool to perform system verification on a programmed device.
Table 6-1 · Designer User Tools
Designer User Tools User Tool Function
Timer Static timing analysis
SmartPower Power analysis
ChipEdit
Customize I/O and logic macro
placements
PinEdit
Customize I/O placements and
attributes
Netlist Viewer View your netlist and trace paths