Actel ProASIC3/E, User Manual, Page: 25 / 106

ProASIC3/E Starter Kit User’s Guide and Tutorial 25
4
Description of Test Design
This description of the test design is provided with the Starter Kit. This design contains a data generator block for
LEDs, clock divider, and an LCD display block. A block diagram of the design is shown in
Figure 4-1 .
Figure 4-1. Design Block Diagram
The clock divider divides the 40 MHz oscillator clock and sends the divided clock to the LCD module and the counter.
The data generator (Data_Block) generates an eight-bit up-down counter and eight-bit flashing signal. The data
generator output is displayed on the ProASIC3E demo board LEDs. You can switch between the data using the SW6
signal. The counter has a synchronous load and an asynchronous clear.
A block diagram of the Data_Block is shown in Figure 4-2 .
Figure 4-2. Data Block Diagram
CLK
SW5
CLK_DIVIDER
CLK
ACLR
DIVIDED_CLK1
DIVIDED_CLK2
0
1
CLK_DIVIDER_instance
SW4
SW1
clk_internal_c
Data_Block
Clock
Updown
Aclr
Sload
Data_select
HexA[3:0]
HexB[3:0]
Data_Block_instance
DATA_LED[7:0]
lcd
clk
reset
lcd_instance
lcd-enable
lcd_rs
lcd_rw
lcd_data[1:4]
SW2
SW3
SW6
HexA[3:0]
HexA[3:0]
0
1
0
1
0
1
0
1
R_nW_LCD
R_nW_LCD
EN_LCD
RS_LCD
RS_LCD
DATA_LCD[7:4]
DATA_LCD[7:4]
LED[7:0]
Clock
Aclr
count8_instance
mux2A[7:0]
A[7:0]
B[7:0]
Y[7:0]
S
DATA_MUX
DATA_LED[7:0]
SW7_count
Data_select
Clock
Updown
Aclr
Sload
HexA[3:0]
HexB[3:0]
Aclr
CLK
Q
LED_Flashing
Q[7:0]
LED_Flashing_instance
count8
Clock
Updown
Aclr
Sload
Data[7:0]