Acromag XMCAP2022, User Manual

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AcroPack Series XMCAP2022 XMC Carrier Board
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board). JTAG is provided for developing applications that use Acromag’s FPGA
AcroPack modules. An adapter cable is available to connect to a Xilinx
Platform USB II programming device (or equivalent). See
Signal Interface
Products for ordering information.
The pin assignment for J3 is shown below. A bypass circuit is included that will
detect a vacant AcroPack site and close a switch to bypass the TDI and TDO
signals. A CPLD on the carrier is included in the JTAG chain. The Xilinx Vivado
tools can detect the presence of the CPLD in the JTAG chain, and skip it when
accessing the FPGAs on the AcroPack modules.
Table 1 JTAG Programming/Debug Connector (J3) Pin Assignment
Signal Pin
TDI 1
TDO 2
GND 3
TCK 4
TMS 5
VREF (3.3V) 6
Notes:
TMS – JTAG Test Mode Select . This pin is the JTAG mode signal establishing
appropriate TAP state transitions for target ISP devices sharing the
same data stream.
TCK – JTAG Test Clock . This pin is the clock signal for JTAG operations and
should be connected to the TCK pin on all target ISP devices sharing the
same data stream.
TDO – JTAG Test Data Out . This pin is the serial data stream received from the
TDO pin on the last device in a JTAG chain.
TDI – JTAG Test Data In . This pin outputs the serial data stream transmitted to
the TDI pin on the first device in a JTAG chain.
V
REF
– The target reference voltage V
REF
is 3.3 Volts
GND – Signal Return